Post-logic isolation of silicon regions for an integrated sensor
View Patent ↗In producing an integrated sensor, regions of silicon between compensating electronics and a sensor are electrically isolated, while the sensor is delineating and released. The described process can be performed at the end of a fabrication process after electronics processing (i.e., CMOS processing) and compensating electronics are formed. In an aspect, the sensor and a conductive bridge are simultaneously developed from a silicon-on-insulator (SOI) substrate. In an aspect, the sensor is undercut from a silicon substrate utilizing a lateral etch. A cavity is concurrently defined by the same lateral etch in the silicon layer, forming the conductive bridge connecting the sensor to a logic component. An isolation trench is defined in the silicon layer between the sensor components and the logic component. A polymer masks vertical surfaces from the lateral etch, and an insulator layer and photosensitive film mask horizontal surfaces from the lateral etch.
1. A method of isolating regions of silicon in producing an integrated sensor comprising:
delineating a sensor from a silicon-on-insulator (SOI) substrate utilizing a trench etch, wherein the SOI substrate comprises a silicon layer situated over a first insulator layer, wherein the first insulator layer is situated over a silicon substrate; and
releasing the sensor utilizing a lateral etch to undercut the sensor from the silicon substrate, wherein a masking agent is used to mask a vertical surface of the silicon layer from the lateral etch, wherein the first insulator layer and a photosensitive film are utilized to mask a horizontal surface of the silicon layer from the lateral etch, and wherein the isolating is performed after fabrication of compensating electronics for the integrated sensor,
wherein delineating the sensor comprises:
etching an open window through a portion of a second insulator layer, exposing the silicon layer;
etching a trench into the silicon layer; and
etching a portion of the first insulator layer, exposing the silicon substrate situated below the first insulator layer.
2. The method as in claim 1 , further comprising, subsequent to etching the first insulator layer:
conformally applying the masking agent over the photosensitive film, the second insulator layer, the silicon layer, the first insulator layer, and the silicon substrate; and
removing the masking agent from a horizontal surface of the photosensitive film, the silicon layer, and the silicon substrate.
3. The method as in claim 1 , farther comprising, prior to etching the first insulator layer:
conformally applying the masking agent over the photosensitive film, the second insulator layer, the silicon layer, and the first insulator layer; and
removing the masking agent from a horizontal surface of the photosensitive film, the silicon layer, the second insulator layer and the first insulator layer.
4. The method as in claim 1 , further comprising removing the masking agent and the photosensitive film from the second insulator layer, the silicon layer, and the first insulator layer.
5. The method as in claim 1 , wherein the trench etch, the lateral etch, a masking agent deposition. a selective removal of the masking agent, and the first insulator etching are performed as individual processes or combinations of processes, and are performed during the same etch run in the same equipment, the equipment comprising a deep reactive ion etch (DRIE) machine.
6. The method as in claim 1 , wherein delineating and releasing the sensor includes forming interdigitated members, cantilevers, mass-and-spring systems, proof masses, rings, capacitor plates, perforations, sensors with symmetric and asymmetric gaps. and laterally and vertically displaced sensor elements.
7. The method as in claim 1 , further comprising, with the delineating and releasing the sensor, simultaneously electrically isolating the sensor by defining a cavity forming a conductive bridge, the conductive bridge connecting the sensor to a logic component, and defining an isolation trench between the sensor and the logic component,
wherein defining the cavity forming the conductive bridge comprises utilizing the lateral etch to etch the silicon substrate and the silicon layer under the conductive bridge, wherein the masking agent masks a vertical surface of a first portion of the silicon layer joined with the sensor from the lateral etch, and the first insulator layer masks a horizontal surface of the first portion of the silicon layer joined with the sensor from the lateral etch, and
wherein defining the isolation trench comprises separating the first portion of the silicon layer joined with the sensor and a second portion of the silicon layer joined with the logic component.
8. The method as in claim 7 , further comprising utilizing a single photolithographic mask, during a single photolithographic masking step, for the sensor delineation, the sensor release, and the electrical isolation.
9. The method as in claim 8 , wherein the compensating electronics comprise CMOS technology.
10. A method of isolating regions of silicon in producing an integrated sensor comprising:
shaping a conductive bridge from a silicon-on-insulator (SOI) substrate, utilizing a trench etch, wherein a silicon layer is situated over a first insulator layer, and the first insulator layer is situated over a silicon substrate; and
defining a cavity under the conductive bridge, the conductive bridge connecting a sensor to a logic component, and defining an isolation trench between the sensor and the logic component,
wherein defining the cavity comprises utilizing a lateral etch to etch the silicon substrate and the silicon layer under the conductive bridge, wherein a masking agent masks a vertical surface of a First portion of the silicon layer joined with the sensor from. the lateral etch, and the first insulator layer and a photosensitive film mask a horizontal surface of the first portion of the silicon layer joined with the sensor from the lateral etch,
wherein defining the isolation trench comprises separating the first portion of the silicon layer joined with the sensor and a second portion of the silicon layer joined with the logic component, and
wherein the isolating is performed after fabrication of compensating electronics for the integrated sensor.
11. The method as in claim 10 , wherein the shaping the conductive bridge comprises:
etching an open window through a portion of a second insulator layer, exposing the silicon layer;
etching a trench into the silicon layer; and
etching a portion of the first insulator layer, exposing the silicon substrate situated below the first insulator layer.
12. The method as in claim 11 , further comprising, subsequent to etching into the first insulator layer:
conformally applying the masking agent over the photosensitive film, the second insulator layer, the silicon layer, the first insulator layer. and the silicon substrate; and
removing the masking agent front a horizontal surface of the photosensitive film, the silicon layer, and the silicon substrate.
13. The method as in claim 11 , further comprising, prior to etching into the first insulator layer:
conformally applying the masking agent over the photosensitive film, the second insulator layer, the silicon layer, and the first insulator layer; and
removing the masking agent from. a horizontal surface of the photosensitive film, the silicon layer, the second insulator layer and the first insulator layer.
14. The method as in claim 11 , wherein the trench etch, the lateral etch, a masking agent deposition, a selective removal of the masking agent, and the first insulator etching are performed as individual processes or combinations of processes, and are performed during the same etch run in the same equipment, the equipment comprising a deep reactive ion etch (DRIE) machine.
15. The method as in claim 10 , further comprising removing the masking agent and the photosensitive film from the conductive layer, the second insulator layer, the silicon layer, -and the first insulator layer.
16. The method as in claim 10 , further comprising, with the shaping the conductive bridge and defining the cavity and the isolation trench, simultaneously delineating die sensor and then releasing the sensor utilizing the lateral etch to undercut the sensor from the silicon substrate, wherein the masking agent is used to mask a vertical surface of the silicon layer from the lateral etch, and the first insulator layer and the photosensitive film are utilized to mask a horizontal surface of the silicon layer from the lateral etch.
17. The method as in claim 16 , further comprising utilizing a single photolithographic mask, during a single photolithographic masking step, for the shaping the conductive bridge, the defining the cavity, the defining the isolation trench, the sensor delineation, and the sensor release.
18. The method as in claim 17 , wherein the compensating electronics comprise CMOS technology.
19. A method of isolating regions of silicon inproducing an integrated sensor comprising:
delineating a sensor from a silicon-on-insulator (SO 1 ) substrate utilizing atrench etch, wherein a silicon layer is situated over a first insulator layer, and thefirst insulator layer is situated over a silicon substrate;
releasing the sensor utilizing a footer undercut etch to undercut the siliconlayer from the first insulator layer; and
lateral etching the silicon substrate, wherein a masking agent is used tomask the silicon layer from the lateral etch, and a photosensitive film is utilized tomask a horizontal surface of the silicon layer from the lateral etch, wherein thefirst insulator layer is etched prior to lateral etching the silicon substrate toexpose the silicon substrate to the lateral etching, and wherein the isolating isperformed after fabrication of compensating electronics for the integrated sensor,
wherein delineating the sensor comprises:
etching an open window through a portion of a second insulator layer,exposing the silicon layer; and
etching a portion of the first insulator layer, exposing the silicon substratesituated below the first insulator layer.
20. The method as in claim 19 , further comprising, subsequent to etching into the first insulator layer:
conformally applying the masking agent over the photosensitive film, the second insulator layer, the silicon layer, the first insulator layer, and the silicon substrate; and
removing the masking agent from a horizontal surface of the photosensitive film, the silicon layer, and the silicon substrate.
21. The method as in claim 19 , further comprising, prior to etching into the first insulator layer:
conformally applying the masking agent over the photosensitive film, the second insulator layer, the silicon layer, and the first insulator layer; and
removing the masking agent from a horizontal surface of the photosensitive film, the silicon layer, the second insulator layer and the first insulator layer.
22. The method as in claim 19 , wherein the trench etch, the footer undercut etch, a masking agent deposition, a selective removal of the masking agent, and the first insulator etching are performed as individual processes or combinations of processes, and are performed during the same etch run in the same equipment, the equipment comprising a deep reactive ion etch (DRIE) machine.
23. The method as in claim 20 , wherein delineating and releasing the sensor includes forming interdigitated members, cantilevers, mass-and-spring systems, proof masses, rings, capacitor plates, perforations, sensors with symmetric and asymmetric gaps, and laterally and vertically displaced sensor elements.
24. The method as in claim 19 , further comprising, with the delineating and releasing the sensor, simultaneously electrically isolating the sensor by defining a cavity forming a conductive bridge, the conductive bridge connecting the sensor to a logic component, and defining an isolation trench between the sensor and the logic component,
wherein defining the cavity forming the conductive bridge comprises utilizing the lateral etch to etch the silicon substrate and the silicon layer under the conductive bridge, wherein the masking agent masks a vertical surface of a first portion of the silicon layer joined with the sensor from the lateral etch, and the first insulator layer masks a horizontal surface of the first portion of the silicon layer joined with the sensor from the lateral etch, and
wherein defining the isolation trench comprises separating the first portion of the silicon layer joined with the sensor and a second portion of the silicon layer joined with the logic component.
25. The method as in claim 24 , further comprising utilizing a single photolithographic mask, during a single photolithographic masking step, for the sensor delineation, the sensor release, and the electrical isolation.
26. The method as in claim 25 , wherein the compensating electronics comprise CMOS technology.