IP Library Granted Patent US 7,474,241
Granted Patent B2
US 7,474,241 · App. 11/733,375 · Granted Jan 6, 2009

Delta-sigma modulator provided with a charge sharing integrator

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,474,241
App. No.
11/733,375
Granted
Jan 6, 2009
Kind
B2
Abstract

An analog-digital delta-sigma converter includes a plurality of continuous time integrators for performing a delta-sigma modulation. Each integrator includes at least one charge sharing integrator at a modulator input. One or more pure integrators follow the charge sharing integrator.

Claims (48)

1. A delta-sigma modulator device comprising:

a first stage comprising at least one charge sharing integrator comprising

an amplifier, and

an integration capacitor including a first terminal connected to an input of said amplifier, and a second terminal connected to an output from said amplifier;

at least one return digital-analog converter; and

a first phase switch coupled between the first terminal of said integration capacitor and said at least one return digital-analog converter, and a second phase switch coupled between the second terminal of the integration capacitor and said at least one return digital-analog converter, said first and second phase switches for applying an output signal from an output of said at least one return digital-analog converter to the first and second terminals of said integration capacitor during a first phase, and for isolating the output from said at least one return digital-analog converter during a second phase.

2. A delta-sigma modulator device according to claim 1 , further comprising at least one additional stage connected to said first stage, said at least one additional stage comprising a transconductance integrator.

3. A delta-sigma modulator device according to claim 1 , wherein said first stage is configured as an input stage of the delta-sigma modulator device.

4. A delta-sigma modulator device according to claim 1 , further comprising at least one quantifier controlled by a sampling clock signal, and wherein said first and second phase switches are controlled by the sampling clock signal.

5. A delta-sigma modulator device according to claim 4 , wherein said at least one return digital-analog converter comprises:

a capacitor for providing the output signal; and

at least one additional switch controlled by the sampling clock signal for applying a voltage to said capacitor during the first phase, with the voltage being produced by said at least one return digital-analog converter;

wherein said first and second phase switches are for connecting said capacitor to said integration capacitor during the second phase.

6. A delta-sigma modulator device according to claim 5 , wherein said capacitor of said at least one return digital-analog converter charges during the first phase, and discharges to said integration capacitor during the second phase.

7. A delta-sigma modulator device comprising:

an input stage comprising at least one charge sharing integrator comprising

an amplifier, and

an integration capacitor including a first terminal connected to an input of said amplifier, and a second terminal connected to an output from said amplifier;

at least one return digital-analog converter comprising

a capacitor for providing an output signal, and

at least one switch for applying a voltage to said capacitor during a first phase, with the voltage being produced by said at least one return digital-analog converter; and

a first phase switch coupled between the first terminal of said integration capacitor and said at least one return digital-analog converter, and a second phase switch coupled between the second terminal of the integration capacitor and said at least one return digital-analog converter, said first and second phase switches for applying the output signal from said capacitor to the first and second terminals of said integration capacitor during the first phase, and for isolating the output from said at least one return digital-analog converter during the second phase.

8. A delta-sigma modulator device according to claim 7 , further comprising at least one additional stage connected to said input stage, said at least one additional stage comprising a transconductance integrator.

9. A delta-sigma modulator device according to claim 7 , further comprising at least one quantifier controlled by a sampling clock signal, and wherein said first and second phase switches are controlled by the sampling clock signal.

10. A delta-sigma modulator device according to claim 9 , wherein said at least one switch is controlled by the sampling clock signal for applying the voltage to said capacitor during the first phase; and wherein said first and second phase switches are for connecting said capacitor to said integration capacitor during the second phase.

11. A delta-sigma modulator device according to claim 10 , wherein said capacitor of said at least one return digital-analog converter charges during the first phase, and discharges to said integration capacitor during the second phase.

12. A digital-analog converter comprising:

at least one delta-sigma modulator device comprising

an input stage comprising at least one charge sharing integrator comprising

an amplifier, and

an integration capacitor including a first terminal connected to an input of said amplifier, and a second terminal connected to an output from said amplifier,

at least one return digital-analog converter, and

a first phase switch coupled between the first terminal of said integration capacitor and said at least one return digital-analog converter, and a second phase switch coupled between the second terminal of the integration capacitor and said at least one return digital-analog converter, said first and second phase switches for applying an output signal from an output of said at least one return digital-analog converter to the first and second terminals of said integration capacitor during a first phase, and for isolating the output from said at least one return digital-analog converter during a second phase; and

a digital processing stage coupled to said at least one delta-sigma modulator device.

13. A digital-analog converter according to claim 12 , wherein said at least one delta-sigma modulator device further comprises at least one additional stage connected to said input stage, said at least one additional stage comprising a transconductance integrator.

14. A digital-analog converter according to claim 12 , wherein said at least one delta-sigma modulator device further comprises at least one quantifier controlled by a sampling clock signal, and wherein said first and second phase switches are controlled by the sampling clock signal.

15. A digital-analog converter according to claim 14 , wherein said at least one return digital-analog converter comprises:

a capacitor for providing the output signal therefrom; and

at least one additional switch controlled by the sampling clock signal for applying a voltage to said capacitor during the first phase, with the voltage being produced by said at least one return digital-analog converter;

wherein said first and second phase switches are for connecting said capacitor to said integration capacitor during the second phase.

16. A digital-analog converter according to claim 15 , wherein said capacitor of said at least one return digital-analog converter charges during the first phase, and discharges to said integration capacitor during the second phase.

17. A method for operating a delta-sigma modulator device comprising an input stage comprising at least one charge sharing integrator comprising an amplifier, and an integration capacitor including a first terminal connected to an input of the amplifier, and a second terminal connected to an output from the amplifier; at least one return digital-analog converter; and a first phase switch coupled between the first terminal of the integration capacitor and the at least one return digital-analog converter, and a second phase switch coupled between the second terminal of the integration capacitor and the at least one return digital-analog converter, the method comprising:

applying via the first and second phase switches an output signal from an output of the at least one return digital-analog converter to the first and second terminals of the integration capacitor during a first phase; and

isolating via the first and second phase switches the output from the at least one return digital-analog converter during a second phase.

18. A method according to claim 17 , wherein the delta-sigma modulator device further comprises at least one additional stage connected to the input stage, the at least one additional stage comprising a transconductance integrator.

19. A method according to claim 17 , wherein the delta-sigma modulator device further comprises at least one quantifier controlled by a sampling clock signal, and wherein the first and second phase switches are controlled by the sampling clock signal.

20. A method according to claim 19 , wherein the at least one return digital-analog converter comprises a capacitor for providing the output signal therefrom; and at least one additional switch controlled by the sampling clock signal for applying a voltage to the capacitor during the first phase, with the voltage being produced by the at least one return digital-analog converter; and wherein the first and second phase switches connect the capacitor to the integration capacitor during the second phase.

21. A method according to claim 20 , wherein the capacitor of the at least one return digital-analog converter charges during the first phase, and discharges to the integration capacitor during the second phase.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED AT REEL: 060161 FRAME: 0346. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 16, 2022
From: FRANCE BREVETS
To: MICROELECTRONIC INNOVATIONS, LLC
Reel/Frame 060389/0768 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2022
From: FRANCE BREVETS
To: MICROELECTRONIC INNOVATIONS, LLC
Reel/Frame 060161/0346 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2016
From: STMICROELECTRONICS INTERNATIONAL NV
To: FRANCE BREVETS
Reel/Frame 039140/0584 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2016
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS INTERNATIONAL NV
Reel/Frame 037841/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2007
From: ANDRE, ERIC
To: STMICROELECTRONICS SA
Reel/Frame 019396/0854 →