IP Library Granted Patent US 7,508,073
Granted Patent B2
US 7,508,073 · App. 11/733,566 · Granted Mar 24, 2009

Wiring board, semiconductor device using the same, and method for manufacturing wiring board

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,508,073
App. No.
11/733,566
Granted
Mar 24, 2009
Kind
B2
Abstract

A wiring board includes: an insulating substrate; a plurality of conductive wirings provided on the insulating substrate so as to be aligned with a semiconductor mounting region where a semiconductor chip is to be mounted; and bump electrodes provided on the respective conductive wirings. The bump electrodes include a first bump electrode for mounting the semiconductor chip and a second bump electrode for adjusting a height of the first bump electrode. The second bump electrode is provided at a region of at least one of the plurality of conductive wirings other than the semiconductor mounting region.

Claims (16)

1. A wiring board, comprising: an insulating substrate; a plurality of conductive wirings provided on the insulating substrate so as to be aligned with a semiconductor mounting region where a semiconductor chip is to be mounted; bump electrodes provided on the respective conductive wirings; and external connection terminals connected to the conductive wiring so as to be connected with an external device,

wherein the bump electrodes comprise first bump electrodes for mounting the semiconductor chip and second bump electrodes for adjusting height of the first bump electrodes,

the first bump electrodes and the second bump electrodes are formed by plating,

at least one of the second bump electrodes is provided at a region of the plurality of conductive wirings outside the semiconductor mounting region so as to be located between the semiconductor mounting region and the external connection terminals, and

the second bump, electrodes protrude from the surface of the conductive wirings in a height direction of the semiconductor chip.

2. The wiring board according to claim 1 ,

wherein some of the conductive wirings at the semiconductor mounting region on the insulating substrate are arranged with a sparse pitch relative to other conductive wirings and the other conductive wirings are arranged with a dense pitch relative to the some of the conductive wirings, and

the second bump electrodes are provided on the some of the conductive wirings that are arranged with the sparse pitch relative to the other conductive wirings.

3. The wiring board according to claim 1 , wherein each of the plurality of conductive wirings is provided with the sonic total number of the first and second bump electrodes.

4. The wiring board according to claim 1 , wherein the second bump electrode is provided at a region other than a region where a package including the semiconductor chip is disposed.

5. The wiring board according to claim 1 , wherein at least one of the plurality of conductive wirings is provided with a plurality of the second bump electrodes.

6. The wiring board according to claim 1 , wherein the second bump electrode is provided at region that is covered with a solder resist film.

7. The wiring board according to claim 1 , wherein the insulating substrate comprises a tape substrate made of a flexible material.

8. A semiconductor device comprising: the wiring board according to claim 1 ; and

a semiconductor chip mounted on the semiconductor mounting region of the wiring board.

9. The wiring board according to claim 1 , wherein all of the second bump electrodes are provided on the conductive wirings at a region outside the semiconductor mounting region so as to be located between the semiconductor mounting region and the external connection terminals.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
CHANGE OF NAME Recorded Nov 21, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0606 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2007
From: NAKAMURA, YOSHIFUMI; SHIMOISHIZAKA, NOZOMI
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 019888/0489 →