Liquid crystal display and thin film transistor array panel therefor

1. A thin film transistor array panel comprising:

a substrate;

a first signal line formed on the substrate and extending in a first wiring layer;

a second signal line formed on the substrate and extending in a second wiring layer to cross with the first signal line;

a first thin film transistor and a second thin film transistor that are respectively connected to the first and the second signal lines;

a pixel electrode that is partitioned to have first and second partitions,

wherein the first and second partitions have respective first and second partition boundary edges, with the first partition boundary edge being spaced apart from and facing the second partition boundary edge,

wherein the first signal line extends underneath the first and second partitions and along a not straight path also disposed under the first and second partitions, and

wherein the first and second spaced apart partition boundary edges of the respective first and second partitions respectively extend along and above opposed sides of the not straight path, and

a connection electrically connecting the first partition and the second partition;

wherein the connection is disposed in the same wiring layer as that of the second signal line.

2. A thin film transistor array panel comprising:

a substrate;

a gate line formed on the substrate and including a gate electrode the gate line extending in a first wiring layer on the substrate;

a gate insulating layer formed on the gate line;

a semiconductor layer formed on the gate insulating layer;

a data line extending in a second wiring layer on the substrate, the data line crossing with the gate line and having a source electrode integrally extending from the data line;

a first drain electrode formed at least partially on the semiconductor layer to be disposed opposite the source electrode;

a passivation layer formed on the semiconductor layer; and

a pixel electrode,

wherein the pixel electrode is partitioned to have first and second partitions,

wherein the first and second partitions have respective first and second partition boundary edges, with the first partition boundary edge being spaced apart from and facing the second partition boundary edge,

wherein the data line extends underneath the first and second partitions and along a not straight path also disposed under the first and second partitions, and

wherein the first and second spaced apart partition boundary edges of the respective first and second partitions respectively extend along and above opposed sides of the not straight path; and

a connection providing an electrical connection between the first partition and the second partition;

wherein the connection is disposed in the same wiring layer as that of the gate line and the connection crosses with the data line.

3. A liquid crystal display comprising:

a first substrate;

a first signal line formed on the first substrate to extend in a first wiring layer of the first substrate;

a second signal line formed on the first substrate to extend in a second wiring layer of the first substrate and to cross with the first signal line;

a first thin film transistor connected to the first and the second signal lines;

a pixel electrode that is partitioned to have first and second partitions,

wherein the first and second partitions have respective first and second partition boundary edges, with the first partition boundary edge being spaced apart from and facing the second partition boundary edge,

wherein the second signal line extends underneath the first and second partitions and along a not straight path also disposed under the first and second partitions, and

wherein the first and second spaced apart partition boundary edges of the respective first and second partitions respectively extend along and above opposed sides of the not straight path;

a second thin film transistor connected to the second partition of the pixel electrode, wherein the first thin film transistor is connected to the first partition of the pixel electrode;

a second substrate facing the first substrate;

a common electrode formed on the second substrate; a liquid crystal layer interposed between the first substrate and the second substrate; and

a domain defining member dividing the liquid crystal layer into a plurality of domains, each domain having two primary edges parallel to corresponding portions of the second signal line;

wherein the liquid crystal layer has negative dielectric anisotropy and is aligned substantially perpendicular to a surface of the first and the second substrates.

4. A liquid crystal display comprising:

a first substrate;

a first signal line formed on the first substrate to extend in a first wiring layer of the first substrate;

a second signal line formed on the first substrate to extend in a second wiring layer of the first substrate and to cross with the first signal line;

a first thin film transistor connected to the first and the second signal lines;

a pixel electrode that is partitioned to have first and second partitions,

wherein the first and second partitions have respective first and second partition boundary edges, with the first partition boundary edge being spaced apart from and facing the second partition boundary edge,

wherein the second signal line extends underneath the first and second partitions and along a not straight path also disposed under the first and second partitions, and

wherein the first and second spaced apart partition boundary edges of the respective first and second partitions respectively extend along and above opposed sides of the not straight path;

a second thin film transistor connected to the second partition of the pixel electrode, wherein the first thin film transistor is connected to the first partition of the pixel electrode;

a second substrate facing the first substrate;

a common electrode formed on the second substrate; a liquid crystal layer interposed between the first substrate and the second substrate; and

a domain defining member dividing the liquid crystal layer into a plurality of domains, each domain having two primary edges parallel to corresponding portions of the second signal line;

wherein the liquid crystal layer has positive dielectric anisotropy and is aligned substantially parallel to a surface of the first and the second substrates and twisted from the first substrate to the second substrate.

5. The thin film transistor array panel of claim 1 ,

wherein the not straight path of the first signal line includes a plurality of angled linear segments including a first angled linear segment that is angled at a first non-parallel and non-orthogonal angle relative to a linear extension direction of the second signal line and a second angled linear segment that is angled at a different second non-parallel and non-orthogonal angle relative to the linear extension direction of the second signal line, and

wherein the connection crosses under an angle change region of the first signal line where the first and second angled linear segments meet.

6. The thin film transistor array panel of claim 1 ,

wherein the first and the second partitions are disposed opposite each other with respect to the first signal line, and

the first and the second thin film transistors are disposed opposite each other with respect to the first signal line.

7. The thin film transistor array panel of claim 1 ,

wherein the first thin film transistor is connected to the first partition of the pixel electrode, and the second partition of the pixel electrode is connected to the second thin film transistor.

8. The thin film transistor array panel of claim 2 ,

wherein the data line includes a plurality of angled linear segments including a first angled linear segment that is angled at a first non-parallel and non-orthogonal angle relative to a linear extension direction of the gate line and a second angled linear segment that is angled at a different second non-parallel and non-orthogonal angle relative to the linear extension direction of the gate line,

wherein the connection crosses under an angle change region of the data line where the first and second angled linear segments meet.

9. The thin film transistor array panel of claim 2 ,

wherein the first and the second partitions are disposed opposite each other with respect to the data line, and

the first and the second drain electrodes are disposed opposite each other with respect to the data line.

10. The thin film transistor array panel of claim 2 ,

wherein the first drain electrode is connected to the first partition of the pixel electrode, and the second partition of the pixel electrode is connected to a second drain electrode.