Cross-point adjustment circuit

1. A circuit for providing cross-point adjustment comprising:

a first input node configured to receive a first data signal;

a second input node configured to receive a second data signal that is the complementary of the first data signal;

a programmable first stage having a first node coupled to the first input node and a second node coupled to the second input node, wherein the programmable first stage is configured to adjust an amount of current provided to the first or second data signals to thereby create a signal offset, wherein the programmable first stage comprises:

a first programmable current supply;

a second programmable current supply;

a first resistor having a first node coupled to the first input node and a second node coupled to the first programmable current supply;

a second resistor having a first node coupled to the second input node and a second node coupled to the second programmable current supply;

a first bipolar transistor having a base terminal coupled to the second node of the first resistor and having an emitter terminal coupled to a first current source;

a second bipolar transistor having a base terminal coupled to the second node of the second resistor and having an emitter terminal coupled to the first current source;

a third resistor having a first terminal coupled to a collector terminal of the first bipolar transistor pair and having a second terminal configured to be coupled to a voltage source when in operation;

a fourth resistor having a first terminal coupled to a collector terminal of the second bipolar transistor and having a second terminal configured to be coupled to the voltage source when in operation;

wherein the collector terminals of the first and second bipolar transistors act as output nodes; and

a second stage having a first node coupled to a third node of the programmable first stage and a second node coupled to a fourth node of the programmable first stage, wherein the second stage is configured to provide the signal offset at a third and fourth node of the second stage to thereby adjust the cross-point of the first and second signals,

wherein the first and second input nodes of the cross-point adjustment circuit are coupled to receive the first and second data signals from an amplifying stage of a post-amplifier in a receiver,

wherein the third and fourth nodes of the second stage are coupled to adjust the cross-point at an input stage of the post-amplifier; and

wherein the first and second programmable current supplies are configured to receive a control signal from a control module specifying the amount of current to adjust, wherein adjusting the first or second programmable current supply causes a signal offset at the collector terminal of the first and second bipolar transistors.

2. The circuit in accordance with claim 1 further comprising a low pass filter having a first node coupled between the third node of the programmable first stage and the first node of the second stage and having a second node coupled between the fourth node of the programmable first stage and the second node of the second stage.

3. The circuit in accordance with claim 2 , wherein the low pass filter comprises at least a capacitor configured to filter fast moving signal components.

4. The circuit in accordance with claim 1 , wherein the programmable first stage includes one or more programmable current supplies configurable to adjust the current provided to the first or second data signals.

5. The circuit in accordance with claim 1 , wherein the programmable first stage is configured to receive a control signal from a control module specifying the amount of current to adjust.

6. The circuit in accordance with claim 1 , further including a rectifying capacitor having a first terminal coupled to the base of the first bipolar transistor and having a second terminal coupled to the base of the second bipolar transistor.

7. The circuit in accordance with claim 1 , wherein the second stage comprises:

an first input node;

a second input node;

a first field effect transistor (VET) having a gate terminal coupled to the first input node and having a source terminal coupled to a current supply;

a second FET transistor having a gate terminal coupled to the second input node and having a source terminal coupled to the current supply;

a first resistor having a first terminal coupled to a drain terminal of the first FET transistor and having a second terminal configured to be coupled to a voltage source when in operation; and

a second resistor having a first terminal coupled to the drain terminal of the second FET transistor and having a second terminal configured to be coupled to the voltage source when in operation.

8. The circuit in accordance with claim 7 , wherein the offset is provided at the drain terminal of the first and second VET transistors.

9. The circuit in accordance with claim 7 , wherein the first and second resistors are 50 ohm termination resistors.

10. A circuit for providing cross-point adjustment comprising:

a first input node configured to receive a first data signal;

a second input node configured to receive a second data signal that is the complementary of the first data signal;

a programmable first stage having a first node coupled to the first input node and a second node coupled to the second input node, wherein the programmable first stage is configured to adjust an amount of current provided to the first or second data signals to thereby create a signal offset, wherein the programmable first stage comprises:

a first programmable current supply;

a second programmable current supply;

a first resistor having a first node coupled to the first input node and a second node coupled to the first programmable current supply;

a second resistor having a first node coupled to the second input node and a second node coupled to the second programmable current supply;

a first VET transistor having a gate terminal coupled to the second node of the first resistor and having an source terminal coupled to a first current source;

a second FET transistor having a gate terminal coupled to the second node of the second resistor and having an source terminal coupled to the first current source;

a third resistor having a first terminal coupled to a drain terminal of the first FET transistor pair and having a second terminal configured to be coupled to a voltage source when in operation;

a fourth resistor having a first terminal coupled to a drain terminal of the second FET transistor and having a second terminal configured to be coupled to the voltage source when in operation;

wherein the drain terminals of the first and second FET transistors act as output nodes;

a second stage having a first node coupled to a third node of the programmable first stage and a second node coupled to a fourth node of the programmable first stage, wherein the second stage is configured to provide the signal offset at a third and fourth node of the second stage to thereby adjust the cross-point of the first and second signals,

wherein the first and second input nodes of the cross-point adjustment circuit are coupled to receive the first and second data signals from an amplifying stage of a post-amplifier in a receiver,

wherein the third and fourth nodes of the second stage are coupled to adjust the cross-point at an input stage of the post-amplifier, and

wherein the first and second programmable current supplies are configured to receive a control signal from a control module specifying the amount of current to adjust, wherein adjusting the first or second programmable current supply causes a signal offset at the drain terminal of the first and second FET transistors.

11. The circuit in accordance with claim 10 , further including a rectifying capacitor having a first terminal coupled to the gate of the first FET transistor and having a second terminal coupled to the gate of the second FET transistor.

12. A circuit for providing cross-point adjustment comprising:

an first input node;

a second input node;

a first programmable current supply;

a second programmable current supply;

a first resistor having a first node coupled to the first input node and a second node coupled to the first programmable current supply;

a second resistor having a first node coupled to the second input node and a second node coupled to the second programmable current supply;

a first bipolar transistor having a base terminal coupled to the second node of the first resistor and having an emitter terminal coupled to a first current source;

a second bipolar transistor having a base terminal coupled to the second node of the second resistor and having an emitter terminal coupled to the first current source;

a third resistor having a first terminal coupled to a collector terminal of the first bipolar transistor pair and having a second terminal configured to be coupled to a voltage source when in operation;

a fourth resistor having a first terminal coupled to a collector terminal of the second bipolar transistor and having a second terminal configured to be coupled to the voltage source when in operation;

a first field effect transistor (VET) having a gate terminal coupled to the collector of the first bipolar transistor and having a source terminal coupled to a second current supply;

a second FET transistor having a gate terminal coupled to the collector terminal of the second bipolar transistor and having a source terminal coupled to the second current supply;

a fifth resistor having a first terminal coupled to a drain terminal of the first FET transistor and having a second terminal configured to be coupled to a second voltage source when in operation; and

a sixth resistor having a first terminal coupled to the drain terminal of the second FET transistor and having a second terminal configured to be coupled to the second voltage source when in operation,

wherein the first and second programmable current supplies are configured to receive a control signal from a control module specifying the amount of current to adjust, wherein adjusting the first or second programmable current supply causes a signal offset at the collector terminal of the first and second bipolar transistors.

13. The circuit in accordance with claim 12 further comprising:

a seventh resistor having a first terminal coupled to the collector of the first bipolar transistor;

an eighth resistor having a first terminal coupled to the collector of the first bipolar transistor; and

a capacitor having a first terminal coupled to a second terminal of the first resistor and the gate terminal of the first FET transistor and having a second terminal coupled to a second terminal of the second resistor and the gate terminal of the second FET transistor, wherein the seventh and eighth resistors and the capacitor act as a low pass filter when in operation.

14. The circuit in accordance with claim 12 , wherein the drain terminal of the first FET transistor is further coupled to a first input node of a post-amplifier and the drain terminal of the second FET transistor is coupled to a second input node of the post-amplifier.

15. The circuit in accordance with claim 12 wherein the signal offset is provided at the drain terminal of the first and second VET transistors to a first and second post-amplifier nodes coupled to the drain terminals of the first and second FET transistors respectively, wherein providing the offset at the drain terminals adjusts the cross-point of an output signal of the post-amplifier.

16. A circuit for providing cross-point adjustment comprising:

an first input node;

a second input node;

a first programmable current supply;

a second programmable current supply;

a first resistor having a first node coupled to the first input node and a second node coupled to the first programmable current supply;

a second resistor having a first node coupled to the second input node and a second node coupled to the second programmable current supply;

a first field effect transistor (VET) transistor having a gate terminal coupled to the second node of the first resistor and having an source terminal coupled to a first current source;

a second FET transistor having a gate terminal coupled to the second node of the second resistor and having an source terminal coupled to the first current source;

a third resistor having a first terminal coupled to a drain terminal of the first FET transistor pair and having a second terminal configured to be coupled to a first voltage source when in operation;

a fourth resistor having a first terminal coupled to a drain terminal of the second FET transistor and having a second terminal configured to be coupled to the first voltage source when in operation;

a third FET having a gate terminal coupled to the drain of the first FET transistor and having a source terminal coupled to a second current supply;

a fourth FET transistor having a gate terminal coupled to the drain terminal of the second FET transistor and having a source terminal coupled to the second current supply;

a fifth resistor having a first terminal coupled to a drain terminal of the third FET transistor and having a second terminal configured to be coupled to a second voltage source when in operation; and

a sixth resistor having a first terminal coupled to the drain terminal of the fourth FET transistor and having a second terminal configured to be coupled to the second voltage source when in operation,

wherein the first and second programmable current supplies are configured to receive a control signal from a control module specifying the amount of current to adjust, wherein adjusting the first or second programmable current supply causes a signal offset at the drain terminal of the first and second VET transistors.

17. The circuit in accordance with claim 16 further comprising:

a seventh resistor having a first terminal coupled to the drain of the first FET transistor;

an eighth resistor having a first terminal coupled to the drain of the first FET transistor and

a capacitor having a first terminal coupled to a second terminal of the first resistor and the gate terminal of the first FET transistor and having a second terminal coupled to a second terminal of the second resistor and the gate terminal of the second FET transistor, wherein the seventh and eighth resistors and the capacitor act as a low pass filter when in operation.

18. The circuit in accordance with claim 16 , wherein the drain terminal of the third FET transistor is further coupled to a first input node of a post-amplifier and the drain terminal of the fourth FET transistor is coupled to a second input node of the post-amplifier.

19. The circuit in accordance with claim 16 , wherein the signal offset is provided at the drain terminal of the third and fourth FET transistors to a first and second post-amplifier nodes coupled to the drain terminals of the third and fourth FET transistors respectively, wherein providing the offset at the drain terminals adjusts the cross-point of an output signal of the post-amplifier.