Method and apparatus for delayed recursion decoder
View Patent ↗A high-speed maximum likelihood sequence estimation method and device. The method includes identifying candidate paths through a state trellis based on a group of observed data, where each candidate path corresponds to a best path through a trellis beginning at one of a possible prior states (and corresponding prior data bit or bits), and then selecting one of the paths based on candidate sequence selection information, typically prior state decisions (e.g., data symbols in the form of one or more bits). The path selection, in turn, provides decoding of symbols and data bit information for use in selecting one of the candidate paths in a subsequent stage.
1. A method comprising:
obtaining, from an analog to digital converter, a plurality of data samples at a plurality of time indices;
calculating, by a branch error metric (BEM) block of a circuit, branch error metrics for the plurality of time indices in response to the plurality of data samples;
calculating, by at least one candidate path identification (CPI) block of the circuit, path metrics in a time-reverse order using the branch error metrics, wherein calculating path metrics in a time-reverse order comprises:
calculating a plurality of end portions of the path metrics, wherein each of the end portions of the path metrics are based on branch error metrics having latest time indices of the plurality of time indices, and wherein each one of the end portions is associated with a respective plurality of symbol sequences;
comparing the plurality of end portions of path metrics to eliminate paths corresponding to the end portions having a large path metric; and
calculating a plurality of earlier portions of the path metrics, wherein each of the earlier portions of the path metrics are based on the end portions of path metrics and on branch error metrics having earlier time indices, and wherein each one of the earlier portions is associated with a respective plurality of symbol sequences;
identifying, by the at least one CPI block of the circuit, a minimum path metric; and,
identifying, by the at least one CPI block of the circuit, a data symbol sequence corresponding to the minimum path metric.
2. The method of claim 1 wherein the step of calculating path metrics in a time-reverse order comprises calculating and comparing end portions of path metrics wherein the end portions are common to a plurality of paths.
3. The method of claim 1 wherein each of the plurality of end portions of the path metrics are a branch metric having a latest time index of the plurality of time indices.
4. The method of claim 1 wherein the step of identifying a minimum path metric includes identifying a plurality of minimum path metrics.
5. The method of claim 1 wherein the data symbol sequence is a trellis coded sequence.
6. The method of claim 1 wherein the data symbol sequence is a sampled version of a channel output signal.
7. The method of claim 1 wherein the at least one CPI block comprises a plurality of CPI blocks.
8. The method of claim 7 wherein the step of calculating branch error metrics includes calculating the branch error metrics for the plurality of candidate path identification blocks.
9. An apparatus comprising:
an integrated circuit including:
an analog to digital converter for providing a plurality of data samples at a plurality of time indices;
a branch error metric logic block for calculating branch error metrics for the plurality of time indices in response to the plurality of data samples; and,
at least one candidate path identification block for calculating path metrics in a time-reverse order using the branch error metrics, identifying a minimum path metric, and identifying a data symbol sequence corresponding to the minimum path metric,
wherein calculating path metrics in a time-reverse order comprises:
calculating a plurality of end portions of the path metrics, wherein each of the end portions of the path metrics are based on branch error metrics having latest time indices of the plurality of time indices, and wherein each one of the end portions is associated with a respective plurality of symbol sequences;
comparing the plurality of end portions of path metrics to eliminate paths corresponding to the end portions having a large path metric; and
calculating a plurality of earlier portions of the path metrics, wherein each of the earlier portions of the path metrics are based on the end portions of path metrics and on branch error metrics having earlier time indices, and wherein each one of the earlier portions is associated with a respective plurality of symbol sequences.
10. The apparatus of claim 9 wherein the at least one candidate path identification block comprises a plurality of candidate path identification blocks connected in a serial fashion.
11. The apparatus of claim 10 wherein an output of one of the plurality of candidate path identification blocks provides an input to another of the plurality of candidate path identification blocks.