Shared memory multi video channel display apparatus and methods
View Patent ↗A scaler positioning module may receive a video signal selected from among a plurality of video signals. The scaler positioning module may include scaler slots for arranging the signal path of the selected video signal through at least one scaler in the scaler positioning module. The scaler slots may enable the scaler positioning module to operate in three modes. The three modes may enable the scaler positioning module to output scaled data without memory operations, scale prior to a memory write, and scale after a memory read. A blank time optimizer (BTO) may receive data from the scaler positioning module at a first clock rate and distributed memory accesses based on a bandwidth requirement determination. The BTO may access memory at a second clock rate. The second clock rate may be slower than the first which may reduce memory bandwidth and enable another video signal to access memory faster.
1. A blank time optimizer comprising:
an input that receives a request from two or more video channels to access a memory, wherein each request has a corresponding data access clock rate; and
circuitry configured to:
store data corresponding to each of the received requests in a shared field line buffer at the data access clock rate of that request;
determine a bandwidth requirement for each request based on the data access clock rate of that request; and
distribute memory accesses based on the bandwidth requirement of each request, wherein the memory accesses are initiated through the shared field line buffer, and wherein the data corresponding to a given request is read out from the shared field line buffer and the memory is accessed at a clock rate different from the data access clock rate of the given request.
2. The optimizer of claim 1 , wherein the circuitry is further configured to overlay two or more video signals from the two or more video channels using the shared field line buffer.
3. The optimizer of claim 1 , wherein the circuitry is further configured to prevent each of the video channels from directly accessing the memory.
4. The optimizer of claim 1 , wherein each request corresponds to a time interval portion of a field line.
5. The optimizer of claim 4 , wherein the circuitry is further configured to distribute the memory access bandwidth by performing a memory operation associated with one of the video signal requests over a time interval portion larger than the time interval portion that corresponds to the requested memory operation.
6. A method for allowing two or more video channels to share access to a memory, the method comprising:
receiving a request from each of the two or more video channels to access the memory, wherein each request has a corresponding data access clock rate;
storing data corresponding to each of the received requests in a shared field line buffer at the data access clock rate of that request;
determining a bandwidth requirement for each of the received requests based on the data access clock rate of that request; and
distributing accesses to the memory based on the bandwidth requirement of each of the received requests, wherein the memory accesses are initiated through the shared field line buffer, and wherein the data corresponding to a given request is read out from the shared field line buffer and the memory is accessed at a clock rate different from the data access clock rate of the given request.
7. The method of claim 6 , further comprising overlaying two or more video signals from the two or more video channels using the shared field line buffer.
8. The method of claim 6 , further comprising preventing each of the video channels from directly accessing the memory.
9. The method of claim 6 , wherein each request corresponds to a time interval portion of a field line.
10. The method of claim 9 , further comprising distributing the accesses to the memory by performing a memory operation associated with one of the video signal requests over a time interval portion larger than the time interval portion that corresponds to the requested memory operation.
11. An apparatus for allowing two or more video channels to share access to a memory means, the apparatus comprising:
means for receiving a request from each of the two or more video channels to access the memory means, wherein each request has a corresponding data access clock rate;
means for storing data corresponding to each of the received requests in a shared field line buffer means at the data access clock rate of that request;
means for determining a bandwidth requirement for each of the received requests based on the data access clock rate of that request;
means for distributing the accesses to the memory means based on the bandwidth requirement of each of the received requests, wherein the memory accesses are initiated through the shared field line buffer means;
means for reading the data corresponding to a given request from the shared field line buffer means; and
means for accessing the memory means at a clock rate different from the data access clock rate of the given request.
12. The apparatus of claim 11 , further comprising means for overlaying two or more video signals from the two or more video channels using the shared field line buffer means.
13. The apparatus of claim 11 , further comprising means for preventing each of the video channels from directly accessing the memory means.
14. The apparatus of claim 11 , wherein each request corresponds to a time interval portion of a field line.
15. The apparatus of claim 14 , further comprising means for distributing accesses to the memory by means for performing a memory operation associated with one of the video signal requests over a time interval portion larger than the time interval portion that corresponds to the requested memory operation.