ELECTRICALLY CONDUCTING TRACK AND METHOD OF MANUFACTURE THEREOF

1 . An electrically conducting track comprising:

an electrically conducting track layer;

a semiconductor substrate; and

a dielectric layer sandwiched between the electrically conducting track layer and the semiconductor substrate;

the electrically conducting track layer further comprising an electrically conducting resistor track between the semiconductor substrate and the dielectric layer.

2 . An electrically conducting track as claimed in claim 1 , wherein the electrically conducting track layer is a bond pad.

3 . An electrically conducting track as claimed in claim 1 , wherein the electrically conducting track layer is a metal.

4 . An electrically conducting track as claimed in claim 1 , wherein the electrically conducting resistor track is a serpentine track comprising at least one bend.

5 . An electrically conducting track as claimed in claim 1 , wherein the resistivity of the electrically conducting resistor track is at least an order of magnitude less than that of the semiconductor substrate.

6 . An electrically conducting track as claimed in claim 5 , wherein the electrically conducting resistor track comprises a metal film on the semiconductor substrate.

7 . An electrically conducting track as claimed in claim 6 , wherein the resistivity of the electrically conducting resistor track is less than 300 ohms per square, preferably less than 200 ohms per square.

8 . An electrically conducting track as claimed in claim 5 , wherein the electrically conducting resistor track comprises a semiconductor resistor track.

9 . An electrically conducting track as claimed in claim 1 , wherein the thickness of the electrically conducting resistor track is less than 300 microns, preferably less than 200 microns.

10 . An electrically conducting track as claimed in claim 1 , wherein the semiconductor substrate is GaAs.

11 . An electrically conducting track as claimed in claim 1 , wherein the semiconductor substrate is Si.

12 . An electrically conducting track as claimed in claim 1 , wherein the dielectric layer is SiN.

13 . An electrically conducting track as claimed in claim 1 comprising a plurality of resistor tracks between the semiconductor substrate and the dielectric layer.

14 . A method of manufacture of an electrically conducting track comprising the steps of:

providing a semiconductor substrate;

providing an electrically conducting resistor track on the semiconductor substrate;

providing a dielectric layer on the semiconductor substrate and the resistor track; and

providing an electrically conducting track layer on the dielectric layer.

15 . A method as claimed in claim 14 , wherein the step of providing an electrically conducting resistor track comprises the step of depositing a metal film on the semiconductor substrate.

16 . A method as claimed in claim 14 , wherein the step of providing a resistor track comprises the step of doping a portion of an upper layer of the semiconductor substrate to improve conductivity of the semiconductor substrate, the doped portion of the semiconductor substrate defining the resistor track.

17 . A method as claimed in claim 14 , wherein the step of providing a resistor track comprises the steps of doping an upper layer of the semiconductor substrate to increase electrical conductivity of the semiconductor substrate, reducing the conductivity of a portion of the upper layer by ion implantation, the remaining portion of the upper layer defining the resistor track.

18 . A method as claimed in claim 14 , wherein the resistor track is serpentine, comprising at least one bend.

19 . A method as claimed in claim 14 , wherein the track layer is a bond pad.

20 . A method as claimed in claim 14 , wherein the track layer is a metal.

21 . (canceled)

22 . (canceled)

23 . (canceled)