PANEL AND SEMICONDUCTOR DEVICE HAVING A STRUCTURE WITH A LOW-K DIELECTRIC
A panel and a semiconductor device, in one embodiment composed of a composite plate with semiconductor chips and plastic housing composition and to a method for producing the same is disclosed. The embodiments include a wiring structure with interconnects and dielectric layers composed of a low-k dielectric is arranged on the top side of the composite plate.
1 . A panel comprising:
a composite; and
a wiring structure having interconnects, and dielectric layers comprised of a low-k dielectric.
2 . The panel of claim 1 , comprising:
the composite plate comprising a plastic housing and semiconductor chips.
3 . The panel of claim 2 , comprising:
where the dielectric layers are arranged on the semiconductor chips.
4 . The panel of claim 1 , comprising:
where the dielectric layers are arranged between the interconnects.
5 . The panel of claim 1 , comprising:
where the interconnects are metallic.
6 . The panel of claim 1 , comprising where the dielectric layers are arranged on a top side of the composite plate.
7 . The panel of claim 1 , comprising:
where the wiring structure is a multilayer wiring structure.
8 . A panel comprising:
a composite plate composed of a plastic housing composition and semiconductor chips arranged in rows and columns on semiconductor device positions;
wherein at least one semiconductor chip having an active top side, a rear side and edge sides is provided per semiconductor device position;
wherein the composite plate has a top side forming a coplanar area with active top sides of the semiconductor chip;
wherein the plastic housing composition embeds the edge sides and the rear side of the semiconductor chip; and
wherein the panel has a mono- or multilayer wiring structure with interconnects and dielectric layers composed of a low-k dielectric on the top side of the composite plate.
9 . The panel of claim 8 , comprising:
where the active top side of each semiconductor chip is surrounded by a frame area composed of plastic housing composition; and
wherein external contact areas are arranged on the frame area, the external contact areas being electrically connected to assigned contact areas on the active top side of the semiconductor chip.
10 . A panel of claim 8 , comprising wherein the panel has the form and dimensions of a semiconductor wafer.
11 . A panel of claim 8 , comprising the external contact areas are formed as test areas for functional tests.
12 . A panel of claim 8 , comprising wherein the external contact areas have surface-mountable external contacts.
13 . A panel of claim 12 , comprising wherein the surface-mountable external contacts have solder balls.
14 . A panel of claim 12 , comprising wherein the surface-mountable external contacts have bonding wires.
15 . A semiconductor device comprising:
a composite; and
a wiring structure having interconnects, and dielectric layers comprised of a low-k dielectric.
16 . The device of claim 15 , comprising:
the composite plate comprising a plastic housing and semiconductor chips.
17 . The device of claim 16 , comprising:
where the dielectric layers are arranged on the semiconductor chips.
18 . The device of claim 15 , comprising:
where the dielectric layers are arranged between the interconnects.
19 . The device of claim 15 , comprising:
where the interconnects are metallic.
20 . The device of claim 15 , comprising where the dielectric layers are arranged on a top side of the composite plate.
21 . A semiconductor device comprising:
one or more semiconductor chips having an active top side, a rear side and edge sides, the semiconductor chips being embedded into a plastic housing composition, wherein the active top side of the semiconductor chip or semiconductor chips forms a coplanar area with parts of the plastic housing composition and the edge sides are embedded into the plastic housing composition; and
wherein a wiring structure with interconnects and dielectric layers composed of a low-k dielectric is arranged on the coplanar area.
22 . The device of claim 21 , further comprising:
wherein the active top side of each semiconductor chip is surrounded by a frame area composed of plastic housing composition, and wherein external contact areas are arranged on the frame area, the external contact areas being electrically connected to assigned contact areas on the active top side of the semiconductor chip.
23 . The device of claim 22 , comprising wherein the external contact areas are formed as test areas for functional tests.
24 . The device of claim 22 , comprising wherein the external contact areas have surface-mountable external contacts.
25 . The device of claim 24 , comprising wherein the surface-mountable external contacts have solder balls.
26 . The device of claim 24 , comprising wherein the surface-mountable external contacts have bonding wires.
27 . A method of producing a semiconductor device comprising:
forming a composite plate having semiconductor chips; and
applying a wiring structure to a top side of the composite plate and an active top side of the composite plate and an active top side of the semiconductor chips, the wiring structure having dielectric layers composed of a low-k dielectric.
28 . The method of claim 27 , comprising:
producing a semiconductor wafer having a multiplicity of semiconductor chip positions arranged in rows and columns;
separating the semiconductor wafer into a multiplicity of semiconductor chips having active top sides, edge sides and rear sides;
populating a carrier with semiconductor chips in semiconductor device positions, the semiconductor chips being fixed by their active top sides on the carrier in rows and columns;
application of a plastic housing composition to the carrier with embedding of the semiconductor chips by their edge sides into the plastic housing composition and with formation of a composite plate having a top side forming a coplanar area with the top sides of the semiconductor chips, with the result that the active top side of each semiconductor chip is surrounded by a frame area composed of plastic housing composition; and
removing the carrier to form a panel.
29 . The method of claim 28 , comprising:
applying contact areas to the active top side of the semiconductor chips;
applying external contact areas to the frame areas;
electrical connecting contact areas to assigned external contact areas; and
separating the panel into individual semiconductor devices.
30 . A method of claim 29 , comprising where in separating the panel into individual semiconductor devices, a functional test of the semiconductor devices is performed via the external contact areas.
31 . A method of claim 29 , comprising wherein the separation of the panel into individual semiconductor devices, external contacts are fitted on the external contact areas.