Method and apparatus for small die low power system-on-chip design with intelligent power supply chip
View Patent ↗A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.
1. A system of cost sensitive die and package design comprising:
an SOC load circuit;
a plurality of sensors coupled to the SOC load circuit for providing information feedback;
a power supply circuit;
a temperature reference coupled to at least one of the plurality of sensors; and
a plurality of actuators coupled to said power supply circuit receiving the information feedback and regulating the power supply circuit according to a power supply intelligence strategy, wherein the temperature reference helps the plurality of sensors coupled to the SOC load circuit provide information feedback to the actuators regulating the power supply circuit according to the power supply intelligence strategy enabling cost sensitive die and package design.
2. The system of claim 1 wherein:
the sensors monitor process corner or temperature.
3. The system of claim 1 wherein:
the system is integrated in a system-in-package format.
4. The system of claim 1 wherein:
the system is integrated in a multi-chip-module format.
5. The system of claim 1 wherein:
the system is monolithically integrated.
6. The system of claim 1 wherein:
the system is comprised of at least two separate chips.
7. The system of claim 1 wherein:
the temperature reference is comprised of a bandgap type temperature reference.