Read-copy-update (RCU) operations with reduced memory barrier usage
View Patent ↗Read-copy-update (RCU) is performed within real-time and other types of systems, such that memory barrier usage within RCU is reduced. A computerized system includes processors, memory, updaters, and readers. The updaters update contents of a section of the memory by using first and second sets of per-processor counters, first and second sets of per-processor need-memory-barrier bits, and a global flip-counter bit. The global flip-counter bit specifies which of the first or second set of the per-processor counters and the per-processor need-memory-barrier bits is a current set, and which is a last set. The readers read the contents of the section of the memory by using the first and second sets of per-processor counters, the first and second sets of per-processor need-memory-barrier bits, and the global flip-counter bit, in a way that eliminates the need for memory barriers during such read operations.
1. A method comprising:
to update contents of a section of memory,
copying a global flip-counter bit to a local flip-counter bit, the global flip-counter bit specifying which of a first set of per-processor counters and a second set of per-processor counters is a current set of per-processor counters and which is a last set of per-processor counters, the global flip-counter-bit also specifying which of a first set of per-processor need-memory-barrier bits and a second set of per-processor need-memory-barrier bits is a current set of per-processor need-memory-barrier bits and which is a last set of per-processor need-memory-barrier bits;
where attempting to acquire a flip-counter-bit lock on the global-flip-counter bit is successful, where the global flip-counter bit has not changed while acquiring the flip-counter-bit lock, where all of the last set of per-processor need-memory-barrier bits are equal to a first predetermined value, and where a sum of all of the last set of per-processor counters is equal to a second predetermined value,
incrementing each of the last set of per-processor need-memory-barrier bits, using the local flip-counter bit;
sending an inter-processor interrupt to execute a memory barrier if needed;
where all of the last set of per-processor need-memory-barrier bits are equal to a second predetermined value,
setting each of the current set of per-processor need-memory-barrier bits to zero, using the local flip-counter bit,
inverting the global flip-counter bit; and,
releasing the flip-counter-bit lock.
2. The method of claim 1 , wherein the first predetermined value is zero and the second predetermined value is two.
3. The method of claim 1 , further comprising, executing a memory barrier before incrementing each of the last set of per-processor need-memory-barrier bits.
4. The method of claim 1 , further comprising, executing a memory barrier before inverting the global flip-counter bit.
5. The method of claim 1 , further comprising, to perform a read-side critical section on the section of memory to read the contents of the section of memory, to acquire an effective read lock in performing the read-side critical section,
incrementing a per-task read-lock-nesting counter corresponding to a task performing the read-side critical section;
where the per-task read-lock-nesting counter is equal to a third predetermined value,
copying the global flip-counter bit to the local flip-counter bit;
incrementing the per-processor counter of the current set of per-processor counters that corresponds to a processor currently executing the task, using the local flip-counter bit; and,
setting a per-task flip-counter bit corresponding to the task equal to the local flip-counter bit.
6. The method of claim 5 , further comprising:
prior to incrementing the per-task read-lock-nesting counter corresponding to the task performing the read-side critical section, disabling preemption and/or interrupts; and,
after setting the per-task flip-counter bit corresponding to the task equal to the local flip-counter bit, enabling preemption and/or interrupts.
7. The method of claim 5 , further comprising, to release the effective read lock in performing the read-side critical section,
decrementing the per-task read-lock-nesting counter corresponding to the task performing the read-side critical section;
where the per-task read-lock-nesting counter is equal to zero,
decrementing the per-processor counter within a set of per-processor counters specified by the per-task flip-counter bit and corresponding to the processor currently executing the task.
8. The method of claim 7 , further comprising:
prior to decrementing the per-task read-lock-nesting counter corresponding to the task performing the read-side critical section, disabling preemption and/or interrupts; and,
enabling preemption and/or interrupts.
9. The method of claim 1 , further comprising periodically performing:
where a per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to a given processor is equal to one,
executing a memory barrier; and,
incrementing the per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to the given processor.
10. The method of claim 1 , further comprising in response to receipt of the inter-processor interrupt:
where a per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to a given processor is equal to one,
executing a memory barrier; and,
incrementing the per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to the given processor.
11. A computerized system comprising:
a plurality of processors;
memory accessible by the processors;
one or more updating tasks to update contents of a section of the memory by using a first set and a second set of per-processor counters, a first set and a second set of per-processor need-memory-barrier bits, and a global flip-counter bit specifying which of the first set or the second set of the per-processor counters and the per-processor need-memory-barrier bits is a current set and which is a last set; and,
one or more reading tasks to read the contents of the section of the memory by using the first set and the second set of per-processor counters, the first set and the second set of per-processor need-memory-barrier bits, and the global flip-counter bit,
wherein no memory barriers are executed by the reading tasks,
and wherein an updating task is to update the contents of the section of the memory by:
copying the global flip-counter bit to a local flip-counter bit;
where attempting to acquire a flip-counter-bit lock on the global-flip-counter bit is successful, where the global flip-counter bit has not changed while acquiring the flip-counter-bit lock, where any of the last set of per-processor need-memory-barrier bits is equal to a value other than zero, and where a sum of all of the last set of per-processor counters is equal to a first predetermined value,
incrementing each of the last set of per-processor need-memory-barrier bits, using the local flip-counter bit;
sending an inter-processor interrupt to execute a memory barrier if needed;
where all of the last set of per-processor need-memory-barrier bits are equal to a second predetermined value,
setting each of the current set of per-processor need-memory-barrier bits to zero, using the local flip-counter bit,
inverting the global flip-counter bit; and,
releasing the flip-counter-bit lock.
12. The computerized system of claim 11 , wherein a reading task is to read the contents of the section of the memory by first acquiring an effective read lock in performing a read operation, by:
incrementing a per-task read-lock-nesting counter corresponding to a task performing the read operation;
where the per-task read-lock-nesting counter is equal to a third predetermined value,
copying the global flip-counter bit to a local flip-counter bit;
incrementing the per-processor counter of the current set of per-processor counters that corresponds to a processor currently executing the task, using the local flip-counter bit; and,
setting a per-task flip-counter bit corresponding to the task equal to the local flip-counter bit.
13. The computerized system of claim 11 , wherein each of the processors if further to periodically:
where a per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to a given processor is equal to one,
executing a memory barrier; and,
incrementing the per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to the given processor.
14. The computerized system of claim 11 , wherein each of the processors if further to, in response to receipt of an inter-processor interrupt:
where a per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to a given processor is equal to one,
executing a memory barrier; and,
incrementing the per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to the given processor.
15. An article of manufacture comprising:
a tangible computer-readable medium storing computer-executable code executable by a processor of a computing device,
wherein the computer-executable code is to update and read a section of memory accessible by a plurality of processors by using a first set and a second set of per-processor counters, a first set and a second set of per-processor need-memory-barrier bits, and a global flip-counter bit specifying which of the first set or the second set of the per-processor counters and per-processor need-memory-barrier bits is a current set and which is a last set,
wherein the computer-executable code does not execute any memory barriers in reading the section of memory,
and wherein the computer-executable code is to update the contents of the section of the memory by:
copying the global flip-counter bit to a local flip-counter bit;
where attempting to acquire a flip-counter-bit lock on the global-flip-counter bit is successful, where the global flip-counter bit has not changed while acquiring the flip-counter-bit lock, where any of the last set of per-processor need-memory-barrier bits is equal to a value other than zero, and where a sum of all of the last set of per-processor counters is equal to a first predetermined value,
incrementing each of the last set of per-processor need-memory-barrier bits, using the local flip-counter bit;
sending an inter-processor interrupt to execute a memory barrier if needed;
where all of the last set of per-processor need-memory-barrier bits are equal to a second predetermined value,
setting each of the current set of per-processor need-memory-barrier bits to zero, using the local flip-counter bit,
inverting the global flip-counter bit; and,
releasing the flip-counter-bit lock.
16. The article of manufacture of claim 15 , wherein the computer-executable code is to read the contents of the section of the memory by first acquiring an effective read lock in performing a read operation, by:
incrementing a per-task read-lock-nesting counter corresponding to a task performing the read operation;
where the per-task read-lock-nesting counter is equal to one,
copying the global flip-counter bit to a local flip-counter bit;
incrementing the per-processor counter of the current set of per-processor counters that corresponds to a processor currently executing the task, using the local flip-counter bit; and,
setting a per-task flip-counter bit corresponding to the task equal to the local flip-counter bit.
17. The article of manufacture of claim 15 , wherein the computer-executable code is further to periodically:
where a per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to a given processor is equal to one,
execute a memory barrier; and,
increment the per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to the given processor.
18. The article of manufacture of claim 15 , wherein the computer-executable code is further to, in response to receipt of an inter-processor interrupt:
where a per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to a given processor is equal to one,
execute a memory barrier; and,
increment the per-processor need-memory-barrier bit of the last set of per-processor need-memory-barrier bits corresponding to the given processor.