Heterogeneous image processing system
View Patent ↗The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a multi-core processor system. To this extent, a multi-core processor system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications referred to herein as an image co-processor that comprises (among other things) a plurality of multi-core processors (MCPs) that work to process multiple images in an accelerated fashion.
1. A heterogeneous image processing system, comprising:
an image co-processor comprising a plurality of distinct multi-core processors (MCPs), the image co-processor being configured to:
receive a plurality of images collectively and substantially simultaneously recorded by a plurality of image recordation mechanisms, each image recordation mechanism providing at least one of the plurality of images for acquisition by one of a plurality of image grabbers;
distribute distinct portions of the plurality of images from each of the image grabbers across the plurality of MCPs, wherein the distinct portions are different views of an object recorded at substantially a same time by at least two of the plurality of image recordation mechanisms; and
collectively and substantially simultaneously process the distinct portions of the plurality of images at the plurality of MCPs to determine associated image data; and
receive a selective off-load of at least one library function at a run time, wherein the at least one library function is written for the plurality of MCPs, wherein the at least one library function supports the processing of the distinct portions of the plurality of images, and wherein the at least one library function is one of a plurality of algorithms, an optimization for a processor architecture, and a wrapper for a scripting language.
2. The heterogeneous image processing system of claim 1 , further comprising a control processor being configured to receive the image data from the image co-processor, and to determine control information for the plurality of images.
3. The heterogeneous image processing system of claim 2 , further comprising:
a staging storage unit for storing the image data for use by the control processor; and
an archive storage unit for storing at least one of the image data or the control information.
4. The heterogeneous image processing system of claim 1 , further comprising an input/output (I/O) processor, the I/O processor comprising:
a set of express peripheral component interconnects (PCIs);
a pure load balancer (PLB) coupled to the set of express PCIs; and
a network interface coupled to the PLB for interfacing with at least one legacy application.
5. The heterogeneous image processing system of claim 4 , the I/O processor receiving the plurality of images from an image grabber, and providing the plurality of images to the image co-processor.
6. The heterogeneous image processing system of claim 1 , the image co-processor further comprising:
a power processing element (PPE); and
an element interconnect bus (EIB) coupled to the PPE and the plurality of MCPs.
7. The heterogeneous image processing system of claim 1 , the MCPs comprising accelerators that increase a rate of processing of the plurality of images.
8. The heterogeneous image processing system of claim 1 , the heterogeneous image processing system being operable with multiple different computing platforms.
9. The heterogeneous image processing system of claim 1 , wherein the different views comprise different angles of view.
10. The heterogeneous image processing system of claim 1 , wherein the different views comprise different perspectives of view.
11. A heterogeneous image processing method, comprising:
receiving a plurality of images in an image co-processor, the image co-processor comprising a plurality of multi-core processors (MCPs), wherein the plurality of images include images collectively and substantially simultaneously recorded by a plurality of image recordation mechanisms, each image recordation mechanism providing at least one of the plurality of images for acquisition by one of a plurality of image grabbers;
distributing distinct portions of the plurality of images from each of the image grabbers across the plurality of MCPs, wherein the distinct portions are different views of an object recorded at substantially a same time by at least two of the plurality of image recordation mechanisms;
processing the distinct portions of the plurality of images collectively and substantially simultaneously with the plurality of MCPs to determine image data associated with the distinct portions of the plurality of images;
providing at least one of the image data or the distinct portions of the plurality of images to a control processor to determine control information associated with the distinct portions of the plurality of images; and
receiving a selective off-load of at least one library function at a run time, wherein the at least one library function is written for the plurality of MCPs, wherein the at least one library function supports the processing of the distinct portions of the plurality of images, and wherein the at least one library function is one of a plurality of algorithms, an optimization for a processor architecture, and a wrapper for a scripting language.
12. The heterogeneous image processing method of claim 11 , further comprising: determining, the control information with the control processor.
13. The heterogeneous image processing method of claim 12 , further comprising:
storing the image data in a staging storage unit for processing by the control processor to determine control information; and
storing at least one of the image data or the control information in an archive storage unit.
14. The heterogeneous image processing method of claim 11 , further comprising:
receiving the plurality of images in an input/output (I/O) processor, the I/O processor comprising:
a set of express peripheral component interconnects (PCIs);
a pure load balancer (PLB) coupled to the set of express PCIs; and
a network interface coupled to the PLB for interfacing with at least one legacy application.
15. The heterogeneous image processing method of claim 14 , the I/O processor receiving the plurality of images from an image grabber, and providing the plurality of images to the plurality of MCPs.
16. The heterogeneous image processing method of claim 11 , the image co-processor further comprising:
a power processing element (PPE); and
an element interconnect bus (EIB) coupled to the PPE and the plurality of MCPs.
17. The heterogeneous image processing method of claim 11 , the plurality of MCPs comprising accelerators that increase a rate of processing of the plurality of images.
18. The heterogeneous image processing method of claim 11 , further comprising receiving the plurality of images in an image grabber from at least one image recording devices.
19. A program product stored on computer readable storage medium for heterogeneously processing an image, the computer readable storage medium comprising program code for causing a computer system to:
receive a plurality of images in an image co-processor, the image co-processor comprising a plurality of multi-core processors (MCPs), wherein the plurality of images include images collectively and substantially simultaneously recorded by a plurality of image recordation mechanisms, each image recordation mechanism providing at least one of the plurality of images for acquisition by one of a plurality of image grabbers;
distribute distinct portions of the plurality of images from each of the image grabbers across the plurality of MCPs, wherein the distinct portions are different views of an object recorded at substantially a same time by at least two of the plurality of image recordation mechanisms;
process the distinct portions of the plurality of images collectively and substantially simultaneously with the plurality of MCPs to determine image data associated with the plurality of images;
provide at least one of the image data or the distinct portions of the plurality of images to a control processor to determine control information associated with the distinct portions of the plurality of images; and
receive a selective off-load of at least one library function at a run time, wherein the at least one library function is written for the plurality of MCPs and wherein the at least one library function is one of a plurality of algorithms, an optimization for a processor architecture, and a wrapper for a scripting language.
20. The program product of claim 19 , the computer readable storage medium further comprising program code for causing the computer system to: determine control information for the plurality of images with the control processor.
21. The program product of claim 20 , the computer readable storage medium further comprising program code for causing the computer system to:
store the image data in a staging storage unit for processing by the control processor; and
store the at least one of the image data or the plurality of images in an archive storage unit.
22. The program product of claim 19 , the computer readable storage medium further comprising program code for causing the computer system to:
receive the plurality of images in an input/output (I/O) processor, the I/O processor comprising:
a set of express peripheral component interconnects (PCIs);
a pure load balancer (PLB) coupled to the set of express PCIs; and
a network interface coupled to the PLB for interfacing with at least one legacy application.
23. The program product of claim 22 , the I/O processor receiving the plurality of images from an image grabber, and providing the plurality of images to the plurality of MCPs.
24. The program product of claim 19 , the image co-processor further comprising:
a power processing element (PPE); and
an element interconnect bus (EIB) coupled to the PPE and the plurality of MCPs.
25. The program product of claim 19 , the MCPs comprising accelerators that increase a rate of processing of the plurality of images.
26. The program product of claim 19 , further comprising receiving the plurality of images in an image grabber from at least one image recording devices.
27. A method for deploying a system for heterogeneously processing an image, comprising:
providing a computer infrastructure being operable to:
receive a plurality of images in an image co-processor, the image co-processor comprising a plurality of multi-core processors (MCPs), wherein the plurality of images include images collectively and substantially simultaneously recorded by a plurality of image recordation mechanisms, each image recordation mechanism providing at least one of the plurality of images for acquisition by one of a plurality of image grabbers;
distribute distinct portions of the plurality of images from each of the image grabbers across the plurality of MCPs, wherein the distinct portions are different views of an object recorded at substantially a same time by at least two of the plurality of image recordation mechanisms;
process the distinct portions of the plurality of images collectively and substantially simultaneously with the plurality of MCPs to determine image data associated with the distinct portions of the plurality of images; and
receive a selective off-load of at least one library function at a run time, wherein the at least one library function is written for the plurality of MCPs, wherein the at least one library function supports the processing of the distinct portions of the plurality of images, and wherein the at least one library function is one of a plurality of algorithms, an optimization for a processor architecture, and a wrapper for a scripting language.