Mask structure for manufacture of trench type semiconductor device
View Patent ↗A mask structure and process for forming trenches in a silicon carbide or other wafer, and for implanting impurities into the walls of the trenches using the same mask where the mask includes a thin aluminum layer and a patterned hard photoresist mask. A thin LTO oxide may be placed between the metal layer and the hard photoresist mask.
1. A hard mask comprising:
a semiconductor wafer;
a hard photoresist mask atop said wafer, wherein said hard photoresist mask comprises a metal layer, and wherein a first portion of said hard photoresist mask resists an etching process; and
a trench gate extending through a second portion of said hard photoresist mask, wherein said trench gate is ion implanted using said first portion of said hard photoresist mask.
2. The hard mask of claim 1 , wherein said hard photoresist mask further comprises:
an oxide layer, wherein said oxide layer is between said metal layer and said wafer.
3. The hard mask of claim 1 , wherein said wafer is silicon carbide.
4. The hard mask of claim 2 , wherein said wafer is silicon carbide.
5. The hard mask of claim 1 , wherein said trench gate extends through said second portion of said hard photoresist mask and a portion of said wafer.
6. The hard mask of claim 5 , wherein said hard photoresist mask further comprises:
an oxide layer, wherein said oxide layer is between said metal layer and said wafer.
7. The hard mask of claim 5 , wherein said wafer is silicon carbide.
8. The hard mask of claim 5 , wherein the walls of said formed trench gate form an angle of 0° to 10° to a vertical line through said formed trench gate which is perpendicular to the plane of said wafer.
9. The hard mask of claim 1 , wherein said metal layer is aluminum having a thickness of from about 0.1 μm to about 1 μm.
10. The hard mask of claim 2 , wherein said oxide layer has a thickness of about 0.1 μm to about 1.0 μm.
11. The hard mask of claim 9 , wherein said oxide layer has a thickness of about 0.1 μm to about 1.0 μm.
12. The process of forming a trench in a semiconductor wafer comprising:
depositing a metal layer atop surface of said wafer;
depositing a photoresist atop said metal layer;
applying a patterned mask atop said photoresist;
photolithographically developing said photoresist to form a hard photoresist mask which contains windows corresponding to the pattern of said mask;
removing portions of said metal layer that are exposed through said windows;
forming a trench into the top surface of said wafer which is exposed after the portions of said metal layer that are removed, wherein a portion of said hard photoresist mask resists etching associated with said forming; and
implanting a controlled impurity into trench walls of said trench using said portion of said hard photoresist mask.
13. The process of claim 12 , wherein said process further comprises:
forming an oxide layer directly atop said wafer surface and directly below said metal layer; and
removing the areas of said oxide layer which are exposed after removal of corresponding areas of said metal layer before forming said trench.
14. The process of claim 12 , wherein said metal layer is aluminum having a thickness of about 0.1 μm to about 1.0 μm.
15. The process of claim 13 , wherein said oxide has a thickness of about 0.1 μm to 1.0 μm.
16. The process of claim 12 , wherein said process further comprises:
masking the surface of said wafer against the implanting by the portion of said hard photoresist mask comprised of said metal layer.
17. The process of claim 13 , wherein said process further comprises:
masking the surface of said wafer against the implanting by the portion of said hard photoresist mask comprised of said metal layer.
18. The mask of claim 1 , wherein said metal layer is selected from the group consisting of aluminum, nickel, tungsten and tantalum and has a thickness of from about 0.1 μm to about 1.0 μm.
19. The process of claim 12 , wherein said metal layer is selected from the group consisting of aluminum, nickel, tungsten and tantalum and has a thickness of from about 0.1 μm to about 1.0 μm.
20. The process of claim 12 further comprising:
removing said photoresist atop said metal layer.
21. The hard mask of claim 1 further comprising:
a photoresist layer formed atop a portion of said metal layer that forms at least one opening wherein said metal layer is exposed.
22. The hard mask of claim 21 further comprising:
a plasma etched portion at said one opening, wherein said plasma etched portion extends to a surface of said semiconductor wafer.
23. The hard mask of claim 1 , wherein a material associated with said hard mask is selected based on ion species and energy associated with said ion to be implanted.