IP Library Granted Patent US 7,736,986
Granted Patent B2
US 7,736,986 · App. 11/740,467 · Granted Jun 15, 2010

Integrated stacked capacitor and method of fabricating same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,736,986
App. No.
11/740,467
Granted
Jun 15, 2010
Kind
B2
Abstract

An integrated stacked capacitor comprises a first capacitor film ( 46 ) of polycrystalline silicide, a second capacitor film ( 48 ) and a first dielectric ( 26 ) sandwiched between the first capacitor film ( 46 ) and second capacitor film ( 48 ). A second dielectric ( 34 ) and a third capacitor film ( 50 ) are provided. The second dielectric ( 34 ) is sandwiched between the second capacitor film ( 48 ) and third capacitor film ( 50 ). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer ( 20 ) to form the first capacitor film ( 46 ); applying a first dielectric ( 26 ); applying a first metallization layer ( 28 ) to form the second capacitor film ( 48 ); applying a second dielectric ( 34 ); and applying a second metallization layer ( 44 ) to form the third capacitor film ( 50 ).

Claims (23)

1. A method for fabrication of a capacitor, comprising the following sequence of steps:

applying a polysilicide layer to form a first capacitor film, wherein said polysilicide layer is applied to an oxide-nitride-oxide layer sequence arranged on a lower polysilicide layer;

applying a first dielectric;

applying a first metallization layer to form a second capacitor film;

applying a second dielectric; and

applying a second metallization layer to form a third capacitor film.

2. The method as set forth in claim 1 , further comprising the step of patterning said polysilicide layer and said lower polysilicide layer so that said lower polysilicide layer protrudes laterally beyond said polysilicide layer.

3. A method for fabrication of a capacitor, comprising the following sequence of steps:

applying a polysilicide layer to form a first capacitor film;

applying a first dielectric;

applying a first metallization layer to form a second capacitor film;

applying a second dielectric;

applying a second metallization layer to form a third capacitor film; and

after application of said first metallization layer:

applying a pre-metal dielectric; and

planarizing said pre-metal dielectric to re-expose said first metallization layer.

4. A method for fabrication of a capacitor, comprising the following sequence of steps:

applying a polysilicide layer to form a first capacitor film;

applying a first dielectric;

applying a first metallization layer to form a second capacitor film;

applying a second dielectric;

applying a second metallization layer to form a third capacitor film; and

applying an etchable stop layer, for chemical-mechanical polishing, to said first dielectric.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2021
From: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 055314/0255 →