IP Library Granted Patent US 7,777,315
Granted Patent B2
US 7,777,315 · App. 11/740,475 · Granted Aug 17, 2010

Dual side cooling integrated power device module and methods of manufacture

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Quick Facts
Patent No.
US 7,777,315
App. No.
11/740,475
Granted
Aug 17, 2010
Kind
B2
Abstract

An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached respectively to the first and second pads, wherein the source of the second transistor is electrically connected to the one or more common source-drain leads. A first clip is attached to the drain of the first transistor and electrically connected to the one or more common source-drain leads. A second clip is attached to the drain of the second transistor and electrically connected to the one or more drain leads located on the outside of the second pad. Molding material encapsulates the lead frame, the transistors, and the clips to form the module.

Claims (30)

1. An integrated transistor module comprising:

a planar lead frame having first and second spaced pads and one or more common source-drain leads located between said first and second pads;

first and second transistors each having source, gate and drain electrodes, attached respectively to top surfaces of said first and second pads, wherein the source electrode of said second transistor is electrically connected to said one or more common source-drain leads; and

a first clip having a planar member and a plurality of downwardly extending leads attached to the drain electrode of said first transistor and electrically connected to said one or more common source-drain leads;

wherein said lead frame, said transistors and said first clip are partially encapsulated in molding material, with a portion of bottom surfaces of each of said first and second pads and said planar member of said clip being exposed to provide dual cooling of said module.

2. The module of claim 1 wherein said first and second transistors are metal oxide semiconductor field effect transistors (MOSFET).

3. The module of claim 1 wherein said first and second transistors are respectively high side and low side power transistors that are components of a buck converter.

4. The module of claim 1 wherein said lead frame includes one or more drain leads located on the outside of said second pad, and including a second clip attached to the drain of said second transistor and electrically connected to said one or more drain leads located on the outside of said second pad.

5. The module of claim 1 wherein said lead frame, said transistors and said clip are partially encapsulated in molding material, with the pads of the lead frame and the clip being exposed to provide dual cooling of said module.

6. An integrated transistor module comprising:

a planar lead frame having first and second spaced pads, one or more common source-drain leads located between said first and second pads, and one or more drain leads located on the outside of said second pad;

first and second transistors attached respectively to top surfaces of said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads;

a first clip having a planar member and a plurality of downwardly extending leads attached to the drain of said first transistor and electrically connected to said one or more common source-drain leads;

a second clip attached to the drain of said second transistor and electrically connected to said one or more drain leads located on the outside of said second pad; and

molding material partially encapsulating said lead frame, said transistors, and said clips to form said module with a portion of the bottom surfaces of each of said first and second pads and both said planar member of said clip being exposed to provide dual cooling of said module.

7. The module of claim 6 wherein said first and second transistors are metal oxide semiconductor field effect transistors (MOSFET).

8. The module of claim 6 wherein said first and second transistors are respectively high side and low side power transistors that are components of a buck converter.

9. The module of claim 6 wherein said one or more common source-drain leads are configured to be cut so that two individual single transistor packages can be formed.

10. The module of claim 6 wherein said lead frame has a gate lead between said first and second pads and wherein said first clip is not electrically attached to said gate lead.

11. The module of claim 6 wherein said second clip has a planar member and a plurality of downwardly extending leads that are electrically connected to said one or more drain leads of said lead frame located on the outside of said second pad.

12. The module of claim 11 wherein said lead frame has a gate lead between said first and second pads and wherein said first clip has no downwardly extending lead to be electrically connected to said gate lead.

13. The module of claim 6 wherein said lead frame is configured to have a leaded footprint which can be converted to a leadless module by cutting off the lead portion of the module.

14. The module of claim 6 wherein said common source drain leads are partially severed to disconnect the connection, and wherein a common heat sink is attached to and connects said first and second clips.

15. The module of claim 6 including an integrated circuit attached to said lead frame and electrically connected to said first and second transistors, said integrated circuit being encapsulated by said molding material to form a single module.

16. An integrated transistor module comprising:

a planar lead frame having first and second spaced source pads, one or more common source-drain leads located between said first and second source pads, and one or more drain leads located on the outside of said second pad;

first and second transistors each with a source electrode on one surface and a drain electrode on the other surface, said first and second source electrodes attached respectively to surfaces of said first and second source pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads;

a first drain clip having a planar member attached to the drain electrode of said first transistor and a plurality of downwardly extending leads electrically connected to said one or more common source-drain leads;

a second drain clip having a planar member attached to the drain electrode of said second transistor and one or more drain leads extending from the planar member and located on the outside of said second pad; and

molding material partially encapsulating said lead frame, said transistors, and said clips to form said module with a portion of the bottom surfaces of each of said first and second source pads and both said planar member of said drain clip being exposed to provide dual cooling of said module.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2008
From: NOQUIL, JONATHAN A.
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 021550/0644 →