Shift register circuit and pull high element thereof

1. A shift register circuit, comprising a plurality of shift registers connected in series, each said shift register comprising:

a phase-shifting element, coupled to a first input, a first clock node and a second clock node, wherein the first input, the first clock node and the second clock node receive a first input signal, a first clock signal and a second clock signal, respectively, and the first clock signal and the second clock signal are complementary in phase; and

a pull-high element, coupled to the phase-shifting element and an output, for pulling up an output signal of the output to a high logic level, wherein the pull-high element comprises a logic unit, and the logic unit has at least two inputs coupled to the phase-shifting element;

wherein

no current path is established in the logic unit when the first input signal is at a low logic level;

the phase-shifting element is configured to determine a first node signal at a first node according to the first input signal and the first clock signal;

the pull-high element is configured to determine a second node signal at a second node according to a second input signal, the first node signal and the second clock signal, and to determine the output signal by the first node signal and the second node signal;

the pull-high element further comprises first, second and third transistors having sources and drains connected in series in the recited order;

the third and second transistors together define the logic unit;

the second node is between the first and second transistors;

a gate of the first transistor is connected to receive the second input signal;

a gate of the third transistor is connected to the second clock node; and

a gate of the second transistor is connected to the first node.

2. The shift register circuit as claimed in claim 1 , wherein the phase-shifting element of each said shift register comprises:

a fourth transistor having a source and a drain connected between the first input and the first node, and a gate connected to the first clock node; and

a fifth transistor having a source and a drain connected between the second clock node and the output, and a gate connected to the first node for receiving the first node signal that determines whether the fifth transistor is turned on or off.

3. The shift register circuit as claimed in claim 2 , wherein the type of transistor of all the transistors is one selected from the group consisting of: PMOS (P-Channel Metal Oxide Semiconductors) and NMOS (N-Channel Metal Oxide Semiconductors).

4. The shift register circuit as claimed in claim 1 , wherein the logic unit of each said shift register is a NAND gate.

5. The shift register circuit as claimed in claim 2 , wherein the pull-high element of each said shift register further comprises:

a sixth transistor;

wherein a gate of the sixth transistor is coupled to the second node, a drain of the sixth transistor is coupled to a first voltage source (VDD) of the high logic level, and a source of the sixth transistor is coupled to the output.

6. The shift register circuit as claimed in claim 5 , wherein the gate of the first transistor is connected to the first clock node to receive the first clock signal as the second input signal.

7. The shift register circuit as claimed in claim 5 , wherein the type of transistor of all the transistors is one selected from the group consisting of: PMOS (P-Channel Metal Oxide Semiconductors) and NMOS (N-Channel Metal Oxide Semiconductors).

8. A pull-high element for pulling up an output signal at an output of the pull-high element to a high logic level, the pull-high element comprising:

first, second and third transistors having sources and drains connected in series in the recited order; and

a fourth transistor;

wherein

the third and second transistors together define a logic unit;

a second node is defined between the first and second transistors;

a gate of the first transistor is connected to receive a second input signal;

a gate of the third transistor is connected to receive a second clock signal;

a gate of the second transistor is connected to receive a first node signal that is determined by a first input signal and a first clock signal;

the second clock signal and the first clock signal are complementary in phase,

no current path is established in the logic unit and the first transistor when the first node signal is at a low logic level;

a gate of the fourth transistor is coupled to the second node for receiving a second node signal,

a drain and a source of the fourth transistor are coupled between a first voltage source (VDD) of a high logic level and the output,

a source of the first transistor is coupled to a second voltage source (VSS) of the low logic level.

9. The pull-high element as claimed in claim 8 , wherein the logic unit is a NAND gate.

10. The pull-high element as claimed in claim 8 , wherein the type of transistor of all the transistors is one selected from the group consisting of: PMOS (P-Channel Metal Oxide Semiconductors) and NMOS (N-Channel Metal Oxide Semiconductors).

11. The pull-high element as claimed in claim 8 , wherein the gate of the first transistor is connected to receive the first clock signal as the second input signal.

12. The pull-high element as claimed in claim 11 , wherein the type of transistor of all the transistors is one selected from the group consisting of: PMOS (P-Channel Metal Oxide Semiconductors) and NMOS (N-Channel Metal Oxide Semiconductors).

13. The pull-high element as claimed in claim 8 , wherein the pull-high element is a pull-high element of in a shift register circuit.