Means to detect a missing pulse and reduce the associated PLL phase bump
A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop.
1. A phase/frequency locked loop (PLL) comprising:
a first flip-flop having a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock;
a second flip-flop having a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock;
a first one-shot block adapted to generate a pulse in response to a rising edge of a reference clock, said reference clock being used to generate the feedback clock, said first one-shot block generating an output signal applied to a reset terminal of the first flip-flop;
a third flip-flop having a data input terminal responsive to the voltage supply, and a clock terminal responsive to the feedback clock;
a fourth flip-flop having a data input terminal responsive to an output of the third flip-flop and a clock terminal responsive to the feedback clock; wherein a reset terminal of the third flip-flop receives the output signal of the first one-shot block; and
a fifth flip-flop having a data input terminal responsive to the voltage supply, and a clock terminal responsive to the inverse of feedback clock;
a sixth flip-flop having a data input terminal responsive to an output of the fifth flip-flop, and a clock terminal responsive to the inverse of the feedback clock; and
a second one-shot block adapted to generate a pulse in response to a falling edge of the reference clock, said second one-shot block generating an output signal applied to a reset terminal of the fifth flip-flop.
2. The PLL of claim 1 further comprising:
a seventh flip-flop having a data input terminal responsive to the voltage supply, and a clock terminal responsive to the feedback clock; and
an eight flip-flop having a data input terminal responsive to an output of the seventh flip-flop and a clock terminal responsive to the feedback clock; wherein a reset terminal of the seventh flip-flop receives the output signal of the second one-shot block.
3. The PLL of claim 2 further comprising:
a first logic gate performing a NOR operation on output signals of the second and fourth flip-flops;
a second logic gate performing a NOR operation on output signals of the sixth and eight flip-flops;
a third logic gate performing a NAND operation on output signals of the first and second logic gates; and
cross-coupled NOR logic responsive to an output of the third logic gate.
4. The PLL of claim 3 wherein reset terminals of the second, fourth, sixth and eight flip-flops are responsive to an reset signal to which said cross-coupled NOR logic is also responsive.
5. The PLL of claim 4 further comprising:
a phase/frequency detector responsive to a phase/frequency of each said feedback and the reference clock;
a first pulse-width limiter adapted to generate a second pulse in response to a first output of the phase/frequency detector;
a second pulse-width limiter adapted to generate a third pulse in response to a second output of the phase/frequency detector; and
a third pulse-width limiter adapted to generate a fourth pulse in response to the reset signal; and
a fourth logic gate performing and OR operation on said second and fourth pulses.
6. The PLL of claim 5 further comprising:
a charge pump responsive to the second pulse and the fourth logic gate; and
an oscillator adapted to generate the feedback clock in response to the charge pump.
7. A method comprising:
supplying a voltage to a data input terminal of a first flip-flop;
applying an output signal of the first flip-flop to a data input terminal of a second flip-flop;
applying an inverse of a feedback clock to clock terminals of the first and second flip-flops;
generating a pulse in response to a rising edge of a reference clock;
generating the feedback clock from the reference clock;
resetting the first flip-flop in response to the pulse;
supplying the voltage to a data input terminal of a third flip-flop;
applying an output signal of the third flip-flop to a data input terminal of a fourth flip-flop;
applying the feedback clock to clock terminals of the third and fourth flip-flops;
resetting the third flip-flop in response to the pulse; and
supplying the voltage to a data input terminal of a fifth flip-flop;
applying an output signal of the fifth flip-flop to a data input terminal of a sixth flip-flop;
applying the inverse of the feedback clock to clock terminals of the fifth and sixth flip-flops; and
resetting the fifth flip-flop in response to the pulse.
8. The method of claim 7 further comprising:
supplying the voltage to a data input terminal of a seventh flip-flop;
applying an output signal of the seventh flip-flop to a data input terminal of an eight flip-flop;
applying the feedback clock to clock terminals of the seventh and eight flip-flops; and
resetting the seventh flip-flop in response to the pulse.
9. The method of claim 8 further comprising:
performing a NOR operation on output signals of the second and fourth flip-flops;
performing a NOR operation on output signals of the sixth and eight flip-flops;
performing a NAND operation on output signals of the first and second logic gates; and
applying a result of the NAND operation to an input of a cross-coupled NOR gate.
10. The method of claim 9 further comprising:
resetting the second, fourth, sixth and eight flip-flops in response to a reset signal; and
applying the reset signal to the cross-coupled NOR gate.
11. The method of claim 10 further comprising:
detecting a difference between phases/frequencies of said feedback and the reference clock;
generating a second pulse in response to the detected difference;
generating a third pulse in response to the detected difference;
generating a third pulse in response to the reset signal; and
performing and OR operation the second and fourth pulses.
12. The method of claim 11 further comprising:
varying a voltage/current level in response to an output of the second pulse and the OR operation; and
generating the feedback clock in response to the varied voltage/current level.