Means to reduce the PLL phase bump caused by a missing clock pulse
View Patent ↗A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.
1. A circuit comprising:
a phase/frequency detector;
a control circuit responsive to the phase/frequency detector and adapted to supply first, second and third control signals, wherein said second control signal is generated after the first control signal is terminated and during a same cycle of a feedback clock signal, and said third control signal is generated after the second control signal is terminated and during the same cycle of a feedback clock signal, wherein a current generated during the second control signal is equal to a sum of currents generated during the first and third control signals, wherein said control circuit comprises:
a first pulse-width limiting circuit adapted to limit a width of a first signal received from the phase/frequency detector so as to generate a first pulse-width limited signal;
a second pulse-width limiting circuit adapted to limit a width of a second signal received from the phase/frequency detector so as to generate a second pulse-width limited signal;
a first slew detector adapted to generate a first slew signal after detecting the first pulse-width limited signal;
a second slew detector adapted to generate a second slew signal after detecting the first slew signal;
a third pulse-width limiting circuit adapted to limit a width of the first slew signal so as to generate a third pulse-width limited signal; and
a fourth pulse-width limiting circuit adapted to limit a width of the second slew signal so as to generate a fourth pulse-width limited signal; and
a charge pump responsive to said first, second and third control signals.
2. The circuit of claim 1 wherein the current generated during the second control signal is twice the current generated during each of the first and third control signals.
3. The circuit of claim 1 wherein said control circuit further comprises:
a first logic gate adapted to generate and apply an OR signal of said first and third pulse-width limited signals to the first charge pump; said first OR signal being representative of the first and third control signals; and
a second logic gate adapted to generate and apply an OR signal of said second and fourth pulse-width limited signals to the first charge pump, said OR signal of the second and fourth signals being representative of the second control signal.
4. The circuit of claim 3 wherein said control circuit is adapted to generate the first, second and third control signals in response to detection of missing pulses of a reference clock.
5. A method of controlling a phase bump of a phased-locked loop, the method comprising:
detecting a difference between a phase of a reference clock signal and a phase of a feedback clock signal;
generating first, second and third control signals in response to the detected difference, wherein said second control signal is generated after the first control signal is terminated and during a same cycle of the feedback signal, and said third control signal is generated after the second control signal is terminated and during a same cycle of the feedback signal;
generating a first current during the first control signal;
generating a second current during the second control signal; and
generating a third current during the third control signal; wherein the current generated during the second control signal is equal to a sum of currents generated during the first and third control signals.
6. The method of claim 5 wherein the current generated during the second control signal is twice the current generated during each of the first and third control signals.
7. The method of claim 5 further comprising:
limiting a width of a first signal received from a phase/frequency detector to generate a first pulse-width limited signal representative of the first control signal;
generating a first slew signal after detecting the first pulse-width limited signal;
generating a second slew signal after detecting the first slew signal;
limiting a width of the first slew signal to generate a third pulse-width limited signal representative of the second control signal; and
limiting a width of the second slew signal to generate a fourth pulse-width limited signal representative of the third control signal.
8. The method of claim 7 further comprising:
generating first, second and third control signals in response to detection of missing pulses of a reference clock.