Systems and Methods for Fabricating Vertical Bipolar Devices
Systems and methods for fabricating bipolar and/or biCMOS devices are described. A combination of bipolar fabrication steps and CMOS, and in particular, SOI fabrication steps may be used. In one embodiment, a collector region and/or a base region of a bipolar device may be formed using a bipolar mask, and an emitter region may be defined by a CMOS mask.
1 . A method comprising:
providing a semiconductor substrate;
depositing a semiconductor insulation layer on the semiconductor substrate;
depositing a hardmask layer on the semiconductor insulation layer;
etching a portion of the hardmask layer to expose a first portion of the semiconductor insulation layer, the etched portion of the hardmask defined by a pattern formed on a voltage threshold mask;
implanting dopants to the exposed first portion of the semiconductor insulation layer to form a collector region;
etching another portion of the hardmask layer to expose a second portion of the semiconductor insulation layer, the another portion of the hardmask layer defined by a pattern formed on a bipolar mask;
implanting dopants to the second portion of the semiconductor insulation layer to form a base region coupled to the collector region; and
defining an emitter region coupled to the base region with a CMOS epitaxial growth process.
2 . The method of claim 1 , further comprising forming an epitaxial growth on the etched second portion of the hardmask layer.
3 . The method of claim 2 , further comprising isolating the epitaxial growth.
4 . The method of claim 3 , the step of isolating the epitaxial growth comprising etching a portion of the epitaxial growth area with an isolation mask.
5 . The method of claim 1 , further comprising forming a base and collector pattern with a CMOS process.
6 . The method of claim 5 , the step of forming a base and collector pattern comprising etching a FIN with a CMOS litho-mask.
7 . The method of claim 1 , further comprising forming spacers for isolating the collector and base region.
8 . The method of claim 1 , the step of defining the emitter region further comprising doping the emitter region with a source-drain implant.
9 . The method of claim 1 , further comprising annealing the vertical bipolar device.
10 . A method comprising:
forming a collector region of a bipolar device using a first bipolar mask;
forming a base region coupled to the collector region using a second bipolar mask; and
forming an emitter region of the bipolar device using a CMOS mask.
11 . The method of claim 10 , the step of forming the collector region comprises:
depositing a hardmask layer on a semiconductor insulation layer of a substrate;
masking the hardmask layer with the first bipolar mask;
etching a first portion of the hardmask layer based on the first bipolar mask to expose a first portion of the semiconductor insulation layer; and
implanting dopants to the exposed first portion of the semiconductor insulation layer to form the collector region.
12 . The method of claim 10 , the step of forming the base region comprising:
masking the hardmask layer with the second bipolar mask;
etching a second portion of the hardmask layer based on the second bipolar mask to expose a second portion of the semiconductor insulation layer; and
implanting dopants to the second portion of the semiconductor insulation layer for forming the base region.
13 . The method of claim 10 , the step of forming the emitter region further comprising doping the emitter region with a source-drain implant.