Method of fabricating thin film transistor substrate and thin film transistor substrate produced using the same
View Patent ↗A method of fabricating a thin film transistor substrate includes forming a gate wiring on an insulating substrate and forming a gate insulating layer on the gate wiring; performing a first hydrogen plasma treatment with respect to the gate insulating layer; forming a first active layer with a first thickness at a first deposition rate on the gate insulating layer; performing a second hydrogen plasma treatment with respect to the first active layer; and forming a second active layer with a second thickness greater than the first thickness at a second deposition rate greater than the first deposition rate, on the first active layer.
1. A method of fabricating a thin film transistor substrate, the method comprising:
forming a gate wiring on an insulating substrate and forming a gate insulating layer on the gate wiring;
performing a first hydrogen plasma treatment with respect to the gate insulating layer;
forming a first active layer with a first thickness at a first deposition rate on the gate insulating layer;
performing a second hydrogen plasma treatment with respect to the first active layer; and
forming, on the first active layer, a second active layer with a second thickness greater than the first thickness at a second deposition rate greater than the first deposition rate,
wherein, in the first active layer subjected to the second hvdrogen plasma treatment, a ratio of a number of Si—H bonds to a number of Si—H 2 bonds is within a range of about 15:1 to about 30:1 .
2. The method of claim 1 , wherein, in the first active layer subjected to the second hydrogen plasma treatment, the ratio of a number of Si—H bonds to a number of Si—H 2 bonds is within a range of about 20:1 to about 25:1.
3. The method of claim 1 , wherein the first active layer is formed within a temperature range of about 150 to about 350° C.
4. The method of claim 1 , wherein the first deposition rate is within a range of about 0.6 to about 1.2 nm/s.
5. The method of claim 1 , wherein the second deposition rate is within a range of about 1.5 to about 2.5 nm/s.
6. The method of claim 1 , further comprising:
sequentially forming a doped amorphous silicon layer and a conductive layer for data wiring on the second active layer; and
patterning the first and second active layers, the doped amorphous silicon layer and the conductive layer for data wiring by using an etching mask.
7. The method of claim 1 , further comprising:
forming a doped amorphous silicon layer;
forming first and second active layer patterns and an ohmic contact layer by pattering the first and second active layers and the doped amorphous silicon layer; and
forming and patterning a conductive layer for data wiring on the ohmic contact layer.
8. The method of claim 1 , wherein, during the second hydrogen plasma treatment, power per unit area applied to a chamber is within a range of about 0.04 to about 0.06 W/cm 2 .
9. The method of claim 8 , wherein, during the second hydrogen plasma treatment, pressure applied to the chamber is within a range of about 1,000 to about 1,600 mT.
10. The method of claim 9 , wherein, during the second hydrogen plasma treatment, hydrogen at a flow rate of about 1,000 to about 2,000 sccm is supplied.
11. The method of claim 10 , wherein, during the second hydrogen plasma treatment, a processing time is within a range of about 60 to about 120 seconds.
12. The method of claim 1 , wherein the first thickness is within a range of about 10 to about 30 nm.
13. The method of claim 12 , further comprising forming a third active layer with a third thickness at the first deposition rate, after the second hydrogen plasma treatment.
14. The method of claim 13 , wherein the third thickness is within a range of about 40 to about 60 nm.
15. The method of claim 1 , wherein the first active layer comprises hydrogenated amorphous silicon.
16. The method of claim 15 , wherein the hydrogenated amorphous silicon is formed by diluting silane with hydrogen.
17. The method of claim 16 , wherein a composition ratio of the silane to the hydrogen is within a range of about 1:4 to 1:8.
18. A thin film transistor substrate comprising:
a gate wiring formed on an insulating substrate;
a gate insulating layer formed on the gate wiring;
a first active layer formed with a first thickness on the gate insulating layer in which a ratio of a number of Si—H bonds to a number of Si—H 2 bonds is within a range of about 15:1 to about 30:1; and
a second active layer formed with a second thickness greater than the first thickness on the first active layer, in which a ratio of a number of Si—H bonds to a number of Si—H 2 bonds is within a range of about 0.1:1 to about 14.9:1.
19. The thin film transistor substrate of claim 18 , wherein the first thickness is within a range of about 10 to about 30 nm.
20. The thin film transistor substrate of claim 19 , further comprising a third active layer formed with a third thickness between the first and second active layers.
21. The thin film transistor substrate of claim 20 , wherein the third thickness is within a range of about 40 to about 60 nm.
22. The thin film transistor substrate of claim 18 , wherein, in the first active layer, the ratio of a number of Si—H bonds to a number of Si—H 2 bonds is within a range of about 20:1 to about 25:1.
23. The thin film transistor substrate of claim 22 , wherein, in the second active layer, the ratio of a number of Si—H bonds to a number of Si—H2 bonds is within a range of about 5:1 to about 6:1.