SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
The semiconductor device includes a silicon substrate, an SiO 2 film provided so as to be in contact with the upper portion of the silicon substrate, and a p-type MOSFET including a polycrystalline silicon film, which is provided so as to be in contact with the upper portion of the SiO 2 film. Further, an interior of the SiO 2 film or an interface of the SiO 2 film with the polycrystalline silicon film is provided with a region containing at least one metallic element of Hf and Zr at an area density of not higher than 1.3×10 14 atoms/cm 2 .
1 . A semiconductor device, comprising a p-type field effect transistor, said p-type field effect transistor comprising:
a semiconductor substrate;
a gate insulating film provided so as to be in contact with an upper portion of said semiconductor substrate; and
a gate electrode provided so as to be in contact with an upper portion of said gate insulating film,
wherein a region is included in said gate insulating film or in an interface between said gate insulating film and said gate electrode, said region containing at least one metallic element of hafnium (Hf) and zirconium (Zr) at an area density of not higher than 1.3×10 14 atoms/cm 2 .
2 . The semiconductor device as set forth in claim 1 , wherein said metallic element is included in said region at an area density of not higher than 5×10 12 atoms/cm 2 .
3 . The semiconductor device as set forth in claim 1 , wherein said gate electrode includes silicon.
4 . The semiconductor device as set forth in claim 1 , wherein said region is a layer containing said metallic element, and a thickness of said layer is equal to or lower than 1 nm.
5 . The semiconductor device as set forth in claim 4 , wherein said layer is provided in an interface between said gate insulating film and said gate electrode.
6 . The semiconductor device as set forth in claim 5 , wherein said gate insulating film is a silicon dioxide (SiO 2 ) film.
7 . The semiconductor device as set forth in claim 4 , wherein said layer is provided in said gate insulating film.
8 . The semiconductor device as set forth in claim 7 , wherein said gate insulating film comprises:
a first gate insulating film provided so as to be in contact with an upper portion of said semiconductor substrate;
said layer provided so as to be in contact with an upper portion of said first gate insulating film; and
a second gate insulating film provided so as to be in contact with an upper portion of said layer.
9 . The semiconductor device as set forth in claim 8 , wherein both of said first gate insulating film and said second gate insulating film are SiO 2 films.
10 . A method for manufacturing the semiconductor device as set forth in claim 1 , comprising:
forming said gate insulating film on said semiconductor substrate;
sputtering at least one metallic element of hafnium (Hf) and zirconium (Zr) onto said gate insulating film to form a region containing said metallic element; and
forming a gate electrode film on said gate insulating film that is provided with said region,
wherein, in said forming said region containing said metallic element, an area density of said metallic element in said region is equal to or lower than 1.3×10 14 atoms/cm 2 .
11 . A method for manufacturing the semiconductor device as set forth in claim 1 , comprising:
forming a first gate insulating film on said semiconductor substrate;
sputtering at least one metallic element of hafnium (Hf) and zirconium (Zr) onto said first gate insulating film to form a region containing said metallic element;
forming a second gate insulating film on said first gate insulating film that is provided with said region; and
forming a gate electrode film on said second gate insulating film,
wherein, in said forming said region containing said metallic element, an area density of said metallic element in said region is equal to or lower than 1.3×10 14 atoms/cm 2 .