Circuits for quiescent current control
View Patent ↗A circuit capable of quiescent current control, the circuit comprising a first operational transconductance amplifier (OTA) including a first output terminal, a first transistor including a first gate coupled to the first output terminal of the first OTA, a second OTA including a second output terminal, a second transistor including a second gate coupled to the second output terminal of the second OTA, a resistive load including a first terminal coupled to the first output terminal and the first gate, and a second terminal coupled to the second terminal and the second gate, a first current source capable of providing a first current flowing toward the first terminal of the resistive load, and a second current source capable of providing a second current flowing away from the second terminal of the resistive load.
1. A circuit capable of quiescent current control, the circuit comprising:
a first operational transconductance amplifier (OTA) including a first output terminal;
a first transistor including a first gate coupled to the first output terminal of the first OTA;
a second OTA including a second output terminal;
a second transistor including a second gate coupled to the second output terminal of the second OTA;
a resistive load including a first terminal coupled to the first output terminal and the first gate, and a second terminal coupled to the second terminal and the second gate;
a first current source capable of providing a first current flowing toward the first terminal of the resistive load; and
a second current source capable of providing a second current flowing away from the second terminal of the resistive load.
2. The circuit of claim 1 , wherein the resistive load includes one of a resistor and a transistor.
3. The circuit of claim 1 , wherein each of the first OTA and the second OTA includes a class AB operational amplifier.
4. The circuit of claim 1 , wherein the first transistor includes a p-type metal-oxide-semiconductor (PMOS) transistor, and the second transistor includes an n-type metal-oxide-semiconductor (NMOS) transistor.
5. The circuit of claim 1 , wherein a voltage across the first terminal and the second terminal of the resistive load is a function of a first offset current flowing toward the first terminal of the resistive load.
6. The circuit of claim 1 , wherein a voltage across the first terminal and the second terminal of the resistive load is a function of a second offset current flowing toward the second terminal of the resistive load.
7. The circuit of claim 1 , wherein a voltage across the first terminal and the second terminal of the resistive load is a function of a first offset current flowing toward the first terminal of the resistive load and a second offset current flowing toward the second terminal of the resistive load.
8. The circuit of claim 1 , wherein the first OTA includes a first input terminal coupled to a reference voltage source, and the second OTA includes a second input terminal coupled to the first input terminal of the first OTA and the reference voltage source.
9. The circuit of claim 1 further comprising a feedback network coupled with the first transistor and the second transistor, the feedback network comprising:
a capacitor;
a first resistor connected in parallel with the capacitor, the first resistor including a first terminal and a second terminal; and
a second resistor coupled between the first terminal and a commode mode voltage source.
10. The circuit of claim 9 , wherein the first terminal of the first resistor is coupled to an inverting input terminal of the first OTA and an inverting input terminal of the second OTA.
11. The circuit of claim 9 , wherein the second terminal of the first resistor is coupled to a drain terminal of the first transistor and a drain terminal of the second transistor.
12. The circuit of claim 1 further comprising a third OTA including a third output terminal coupled to the first output terminal of the first OTA.
13. The circuit of claim 1 further comprising a fourth OTA including a fourth output terminal coupled to the second output terminal of the second OTA.
14. A circuit capable of quiescent current control, the circuit comprising:
a pair of transistors capable of providing an output voltage, each of the pair of transistors including a gate terminal;
a pair of operational amplifiers capable of driving the pair of transistors; and
a control circuit including a pair of current sources and a resistive load between the pair of current sources,
wherein a voltage across the gate terminals of the pair of transistors is a function of an offset current flowing from at least one operational amplifier of the pair of operational amplifiers through the resistive load.
15. The circuit of claim 14 , wherein the pair of operational amplifiers includes a first operational transconductance amplifier (OTA) including a first output terminal, and a second OTA including a second output terminal.
16. The circuit of claim 15 , wherein the pair of transistors includes a first transistor including a first gate coupled to the first output terminal of the first OTA, and second transistor including a second gate coupled to the second output terminal of the second OTA.
17. The circuit of claim 14 , wherein the resistive load includes one of a resistor and a transistor.
18. The circuit of claim 16 , wherein the resistive load includes a first terminal coupled to the first output terminal and the first gate, and a second terminal coupled to the second terminal and the second gate.
19. The circuit of claim 18 , wherein the pair of current sources includes a first current source capable of providing a first current flowing toward the first terminal of the resistive load.
20. The circuit of claim 18 , wherein the pair of current sources includes a second current source capable of providing a second current flowing away from the second terminal of the resistive load.
21. The circuit of claim 18 , wherein a voltage across the first terminal and the second terminal of the resistive load is a function of a first offset current flowing toward the first terminal of the resistive load.
22. The circuit of claim 18 , wherein a voltage across the first terminal and the second terminal of the resistive load is a function of a second offset current flowing toward the second terminal of the resistive load.
23. The circuit of claim 14 further comprising a feedback network coupled with the first transistor and the second transistor, the feedback network comprising:
a capacitor;
a first resistor connected in parallel with the capacitor, the first resistor including a first terminal and a second terminal; and
a second resistor coupled between the first terminal and a commode mode voltage source.
24. The circuit of claim 15 further comprising a third OTA including a third output terminal coupled to the first output terminal of the first OTA.
25. The circuit of claim 15 further comprising a fourth OTA including a fourth output terminal coupled to the second output terminal of the second OTA.
26. A circuit capable of quiescent current control, the circuit comprising:
a first operational transconductance amplifier (OTA) including a first output terminal;
a second OTA including a second output terminal;
a resistive load including a first terminal coupled to the first output terminal of the first OTA, and a second terminal coupled to the second terminal of the second OTA;
a first current source capable of providing a first current flowing toward the first terminal of the resistive load; and
a second current source capable of providing a second current flowing away from the second terminal of the resistive load,
wherein a voltage across the first terminal and the second terminal of the resistive load is a function of an offset current flowing from at least one of the first OTA and the second OTA through the resistive load.
27. The circuit of claim 26 , wherein the resistive load includes one of a resistor and a transistor.
28. The circuit of claim 26 further comprising a PMOS transistor including a gate coupled to the first terminal of the resistive load, and an NMOS transistor including a gate coupled to the second terminal of the resistive load.
29. The circuit of claim 26 further comprising a third OTA including a third output terminal coupled to the first output terminal of the first OTA.
30. The circuit of claim 26 further comprising a fourth OTA including a fourth output terminal coupled to the second output terminal of the second OTA.