Scan flip-flop with internal latency for scan input

1. A scan flip-flop circuit comprising:

a data input;

a scan input;

a data output;

a flip-flop providing an output signal at said data output of said scan flip-flop circuit;

a multiplexer, for selecting a signal at one of said scan input and said data input, for presentation at an input of said flip-flop;

said multiplexer comprising a delay element, in a signal path between said scan input and said input of said flip-flop, to provide a signal propagation delay between said scan input and said input of said flip-flop, that is in excess of a signal propagation delay between said data input and said input of said flip-flop; and wherein said multiplexer comprises:

(a) a first PMOS-AND structure comprising a plurality of PMOS transistors interconnected in series; and

(b) a first NMOS-AND structure comprising a plurality NMOS transistors interconnected in series;

and wherein said first NMOS-AND structure is connected between said first PMOS-AND structure and electrical ground; and said first PMOS-AND structure is interconnected between a supply voltage and said first NMOS-AND structure; and

wherein said delay element comprises at least one of

(i) a PMOS diode interconnected to two of said PMOS transistors in said first PMOS-AND structure; and

(ii) an NMOS diode interconnected to two of said NMOS transistors in said first NMOS-AND structure.

2. The scan flip-flop circuit of claim 1 , wherein said multiplexer is formed as a complementary metal oxide semiconductor (CMOS) circuit, comprising p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs).

3. The scan flip-flop circuit of claim 2 , further comprising a scan-enable input, wherein said multiplexer selects said signal at one of said scan input and said data input for presentation at said input of said flip-flop, in response to a scan-enable signal at said scan-enable input.

4. The scan flip-flop circuit of claim 1 , wherein said multiplexer further comprises:

(i) a second PMOS-AND structure comprising a set of PMOS transistors interconnected in series; and

(ii) a second NMOS-AND structure comprising a set of NMOS transistors interconnected in series;

said second NMOS-AND structure placed between said second PMOS-AND structure and electrical ground; said second PMOS-AND structure placed between a supply voltage and said second NMOS-AND structure.

5. The scan flip-flop circuit of claim 4 , wherein said first PMOS-AND structure comprises a first input accepting a signal at said scan input and a second input accepting a complement of a signal at said scan-enable input.

6. The scan flip-flop circuit of claim 4 , wherein said first NMOS-AND structure comprises a first input accepting a signal at said scan input and a second input accepting a signal at said scan-enable input.

7. The scan flip-flop circuit of claim 5 , wherein said first PMOS-AND structure comprises a first PMOS FET interconnected to a second PMOS FET by said PMOS diode; and wherein said first input comprises a gate of said first PMOS FET and said second input comprises a gate of said second PMOS FET.

8. The scan flip-flop circuit of claim 6 , wherein said first NMOS-AND structure comprises a first NMOS FET interconnected to a second NMOS FET by said NMOS diode; and wherein said first input comprises a gate of said first NMOS FET and said second input comprises a gate of said second NMOS FET.

9. The scan flip-flop circuit of claim 4 , wherein said second PMOS-AND structure has a first input and a second input, and comprises a first PMOS FET interconnected a second PMOS FET; and wherein said first input comprises a gate of said first PMOS FET and said second input comprises a gate of said second PMOS FET.

10. The scan flip-flop circuit of claim 4 , wherein said second NMOS-AND structure has a first input and a second input, and comprises a first NMOS FET interconnected a second NMOS FET; and wherein said first input comprises a gate of said first NMOS FET and said second input comprises a gate of said second NMOS FET.

11. The scan flip-flop circuit of claim 1 , wherein said delay element provides a delay of about 30 ps to 120 ps.

12. The scan flip-flop circuit of claim 4 , further comprising a regenerating block comprising:

a third PMOS-AND structure connected between said power supply and a drain terminal of said PMOS diode; and

a third NMOS-AND structure connected between a drain terminal of said NMOS diode and said electrical ground.

13. The scan flip-flop circuit of claim 12 , wherein

said third PMOS-AND structure comprises a first PMOS FET accepting a signal at said scan input at its gate, connected in series with a second PMOS FET accepting a signal a said input of said flip-flop at its gate.

14. The scan flip-flop circuit of claim 13 , wherein

said third NMOS-AND structure comprises a first NMOS FET accepting a signal at said input of said flip-flop at its gate, connected in series with a second NMOS FET accepting a signal at said scan input, at its gate.

15. The scan flip-flop circuit of claim 12 , wherein said regenerating block forces a signal level presented at said input of said flip-flop to be at said electrical ground when said signal presented at said input of said flip-flop is set high.

16. The scan flip-flop circuit of claim 12 , wherein said regenerating block forces a signal level at said input of said flip-flop to be at said supply voltage when said signal presented at said input of said flip-flop is low.

17. A method of operating a scan flip-flop circuit, said scan flip-flop circuit comprising a data signal input for receiving a data signal, a scan input for receiving a scan signal and a clock input for receiving a clock signal, said method comprising:

receiving said scan signal at said scan input;

receiving said clock signal at said clock input;

providing said data signal input and said scan signal input to a multiplexer;

said multiplexer comprising a delay element, in a signal path between said scan input and said input of said flip-flop, to provide a signal propagation delay between said scan input and said input of said flip-flop, that is in excess of a signal propagation delay between said data input and said input of said flip-flop; and wherein said multiplexer comprises:

(a) a first PMOS-AND structure comprising a plurality of PMOS transistors interconnected in series; and

(b) a first NMOS-AND structure comprising a plurality NMOS transistors interconnected in series;

and wherein said first NMOS-AND structure is connected between said first PMOS-AND structure and electrical ground; and said first PMOS-AND structure is interconnected between a supply voltage and said first NMOS-AND structure; and

wherein said delay element comprises at least one of

(i) a PMOS diode interconnected to two of said PMOS transistors in said first PMOS-AND structure; and

(ii) an NMOS diode interconnected to two of said NMOS transistors in said first NMOS-AND structure;

providing said clock signal to a flip-flop;

selecting said scan signal using said multiplexer, for presentation at an input of said flip-flop;

introducing a delay in said multiplexer using said delay element; and

providing an output of said flip-flop as an output signal of said circuit.

18. The method of claim 17 , wherein said delay introduced inside said multiplexer is about 30 ps to 120 ps.

19. The method of claim 17 , wherein said multiplexer is formed as a CMOS circuit, comprising PMOS FETs and NMOS FETs.

20. The method of claim 19 , further comprising receiving a scan-enable signal wherein said selecting said scan signal is performed in response to said scan-enable signal.

21. The method of claim 20 , further comprising forcing a signal level of a signal presented at said input of said flip-flop to be at one of a supply voltage and electrical ground, using a regenerating block.