IP Library Granted Patent US 7,777,656
Granted Patent B2
US 7,777,656 · App. 11/749,191 · Granted Aug 17, 2010

Decoding, encoding/decoding and converting

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Quick Facts
Patent No.
US 7,777,656
App. No.
11/749,191
Granted
Aug 17, 2010
Kind
B2
Abstract

Implementations and embodiments of decoders, encoder/decoder systems and converters are depicted and described.

Claims (48)

1. A decoder comprising:

an input to receive a time-encoded signal;

a filter which is coupled to the input;

a sampler which has a signal input which is coupled to an output of the filter;

an edge detector, comprising an input coupled to the input of the decoder, and comprising an output coupled to a clock signal input of the sampler; and

an asynchronous to synchronous converter, comprising a signal input coupled to the output of the sampler, and an output coupled to an output of the decoder.

2. The decoder according to claim 1 , further comprising an interpolator coupled to the sampler.

3. A converter comprising:

an input;

an output; and

a encoding/decoding system, the encoding/decoding system comprising:

an encoder to generate a time encoded input signal;

a decoder comprising an input coupled to an output of the encoder, the decoder comprising:

an edge detector, comprising an input coupled to the input of the decoder;

a first sampler, comprising a signal input coupled to the input of the decoder and a clock signal input coupled to an output of the edge detector; and

an asynchronous to synchronous converter, comprising an input coupled to the output of the first sampler, and an output coupled to an output of the encoding/decoding system.

4. The converter according to claim 3 , wherein an out-put of the encoding/decoding system is also coupled via a backward path to the input of the encoding/decoding system.

5. The converter according to claim 3 , wherein the encoder comprises a first and second loop filter.

6. The converter according to claim 3 , wherein the converter comprises a first and second feedback loop.

7. The converter according to claim 3 , wherein the encoder comprises a second sampler.

8. The converter according to claim 3 , wherein the first and second sampler are implemented to operate at a first oversampling rate.

9. The converter according to claim 3 , wherein the asynchronous to synchronous converter is further implemented to decimate the oversampling rate of the output signal of the converter from the first oversampling rate to a second oversampling rate.

10. The converter according to claim 3 , wherein the encoder comprises a loop filter, and the decoder comprising a filter simulating a filter function of the loop filter.

11. A converter comprising:

an input to receive an analog signal;

an output to provide a digital signal;

a first encoding circuit coupled to the input, the first circuit comprising a self-oscillating pulse width modulator to provide an oversampled single-bit signal with an oversampling frequency;

a second decoding circuit coupled to the first circuit to receive the oversampled single-bit signal and configured to provide a digital signal with a sampling frequency lower than the oversampling frequency to the output;

a feedback path coupled to the first circuit to feed back to the noise shaping filter an analog signal based on the over-sampled single-bit signal.

12. The converter according to claim 11 , wherein the noise shaping filter is a higher-order noise shaping filter.

13. The converter according to claim 11 , wherein the noise shaping filter is coupled via a digital-to-analog converter to the first circuit.

14. The converter according to claim 11 , wherein the second circuit comprises a filter having a filter function with a zero at the limit cycle frequency of the self-oscillating pulse width modulator.

15. The converter according to claim 11 , wherein the noise shaping filter is implemented to shape a quasi-periodic signal concentrated at a predetermined frequency.

16. The converter according to claim 11 , wherein the feedback path is a feedback path of the self-oscillating pulse width modulator and the noise shaping filter and a loop filter of the self-oscillating pulse width modulator are implemented in a same loop filter.

17. The converter according to claim 11 , wherein the feed back path comprises a single bit digital-to-analog converter coupled to the first circuit to receive the oversampled single-bit signal and coupled to the noise shaping filter to provide an analog signal based on the oversampled single-bit signal.

18. A converter comprising:

an input to receive an analog signal;

an output to provide a digital signal;

a first circuit coupled to the input, the first circuit comprising a self-oscillating pulse width modulator to provide an oversampled single-bit signal with an oversampling frequency, the self-oscillating pulse width modulator comprising a first feedback path and a loop filter;

a second decoding circuit coupled to the first circuit to receive the oversampled single-bit signal and configured to provide a decoded digital signal with a sampling frequency lower than the oversampling frequency to the output; and

a noise shaping filter; and

a second feedback path to feed back an analog signal based on the oversampled single-bit signal to the noise shaping filter.

19. The converter according to claim 18 , wherein the noise shaping filter is implemented in a feed forward path of the first circuit between the input and the self-oscillating pulse width modulator.

20. The converter according to claim 18 , wherein the second decoding circuit comprises a digital filter with a filter function, the filter function having a zero corresponding to the limit cycle frequency of the self-oscillating pulse width modulator.

21. The converter according to claim 18 , wherein the second decoding circuit comprises a digital decimator filter with a filter function corresponding to a filter function of the loop filter.

22. The converter according to claim 18 , wherein the noise shaping filter is implemented in a feed forward path of the first circuit.

23. The converter according to claim 18 , further comprising a single-bit digital-to-analog converter coupled between an output of the first encoding circuit and the loop filter.

24. The converter according to claim 18 , wherein an input of the noise shaping filter is coupled to an output of the loop filter.

Assignments (6)
SECURITY AGREEMENT Recorded Jul 9, 2021
From: MAXLINEAR, INC.; MAXLINEAR COMMUNICATIONS, LLC; EXAR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 056816/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2020
From: INTEL CORPORATION
To: MAXLINEAR, INC.
Reel/Frame 053626/0636 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2020
From: LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: INTEL CORPORATION
Reel/Frame 053259/0678 →
MERGER AND CHANGE OF NAME Recorded Jan 17, 2018
From: LANTIQ DEUTSCHLAND GMBH; LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 045085/0292 →
MERGER Recorded Dec 18, 2017
From: LANTIQ DEUTSCHLAND GMBH
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 044907/0045 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 025413/0340 AND 025406/0677 Recorded Apr 17, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 035453/0712 →