Metal-oxide-semiconductor high electron mobility transistors and methods of fabrication
View Patent ↗A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described.
1. A metal oxide semiconductor (MOS) transistor, comprising:
a Group III-V semiconductor substrate;
a first recess;
an oxide layer disposed in the first recess and over a channel;
a plated gate disposed over the oxide layer and in a second recess;
a seed layer disposed between the plated gate and the oxide layer; and
a barrier layer disposed between the seed layer and the oxide layer, wherein said barrier layer comprises a refractory metal and a refractory metal alloy.
2. A MOS transistor as claimed in claim 1 , further comprising a plurality of epitaxial layers disposed between the oxide layer and the substrate, wherein one of the layers includes the channel.
3. A MOS transistor as claimed in claim 2 , wherein the channel is a buried channel and the transistor is a high electron mobility transistor (HEMT).
4. MOS transistor as claimed in claim 1 , wherein the gate is aligned with the first recess.