Verification of memory consistency and transactional memory

1. A system, comprising:

a test module operable to coordinate execution of a test program on a test platform; and

an analysis module, wherein the analysis module is configured to:

represent memory operations performed during the execution as nodes of a directed graph;

add edges to the directed graph representing ordering relationships between the memory operations;

traverse one or more existing edges of a directed graph, starting from a first node of the directed graph, to infer whether an additional edge is to be added to the directed graph;

perform a backtracking procedure to return to a prior choice point and make an alternate choice, if additional edges are not inferred; and

detect that a memory consistency model is violated if a cycle is found in the directed graph.

2. The system as recited in claim 1 , wherein the analysis module is further configured to:

utilize a first set of rules to verify that results of the execution correspond to a valid ordering of events, if the test platform provides an indication of an order in which writes from multiple processing elements of a plurality of processing elements are performed at a shared memory location during the execution; and

utilize a second set of rules to verify that the results correspond to a valid ordering of events, if the test platform does not provide an indication of the order.

3. The system as recited in claim 2 , wherein the analysis module is further operable to utilize transactional memory axioms to verify the memory consistency model.

4. The system as recited in claim 3 , wherein said transactional memory axioms are selected from a group consisting of: a program order within a transaction implies global order; memory barriers are implicit around each transaction; and no other memory operations can intervene between two consecutive operations in a transaction.

5. The system as recited in claim 2 , wherein, if the test platform does not provide an indication of the order, the analysis module is further configured to:

use a heuristic based on a possible write order at each shared memory location of a plurality of shared memory locations to determine whether the results correspond to a valid ordering of events according to the memory consistency model.

6. The system as recited in claim 1 , wherein the test platform includes a simulation model of a multiprocessor system.

7. The system as recited in claim 1 , wherein the test platform includes a multiprocessor system.

8. The system as recited in claim 1 , wherein the test module is further configured to generate a multithreaded test program.

9. The system as recited in claim 8 , wherein the test module is further configured to include a mix of instructions in the multithreaded test programs in accordance with user-specified input parameters.

10. The system as recited in claim 8 , wherein each write operation included in the multithreaded test program writes a distinctly identifiable value.

11. A method, comprising:

coordinating an execution of a multithreaded test program on a test platform including a plurality of processing elements;

representing memory operations performed during the execution as nodes of a directed graph;

adding edges to the directed graph representing ordering relationships between the memory operations;

traversing one or more existing edges of a directed graph, staffing from a first node of the directed graph, to infer whether an additional edge is to be added to the directed graph;

performing a backtracking procedure to return to a prior choice point and make an alternate choice, if additional edges are not inferred; and

detecting that a memory consistency model is violated if a cycle is found in the directed graph.

12. The method as recited in claim 11 , further comprising:

if the test platform provides an indication of an order in which writes from multiple processing elements of the plurality of processing elements are performed at a shared memory location during the execution, using a first set of rules to verify that results of the execution correspond to a valid ordering of events according to a memory consistency model; and

if the test platform does not provide an indication of the order, using a second set of rules to verify that the results correspond to a valid ordering of events according to the memory consistency model.

13. The method as recited in claim 12 , further comprising utilizing transactional memory axioms to verify the memory consistency model.

14. The method as recited in claim 13 , wherein said transactional memory axioms are selected from a group consisting of: a program order within a transaction implies global order; memory barriers are implicit around each transaction; and no other memory operations can intervene between two consecutive operations in a transaction.

15. The method as recited in claim 11 , further comprising:

if the test platform does not provide an indication of the order, using a heuristic based on a possible write order at each shared memory location of a plurality of shared memory locations to determine whether the results correspond to a valid ordering of events according to the memory consistency model.

16. A computer readable storage medium comprising software instructions, wherein the software instructions are executable by a processor to:

coordinate an execution of a multithreaded test program on a test platform including a plurality of processing elements;

represent memory operations performed during the execution as nodes of a directed graph;

add edges to the directed graph representing ordering relationships between the memory operations;

traverse one or more existing edges of a directed graph, starting from a first node of the directed graph, to infer whether an additional edge is to be added to the directed graph;

perform a backtracking procedure to return to a prior choice point and make an alternate choice, if additional edges are not inferred; and

detect that a memory consistency model is violated if a cycle is found in the directed graph.

17. The computer readable storage medium as recited in claim 16 , wherein the instructions are further executable to:

if the test platform provides an indication of an order in which writes from multiple processing elements of the plurality of processing elements are performed at a shared memory location during the execution, use a first set of rules to verify that results of the execution correspond to a valid ordering of events according to a memory consistency model; and

if the test platform does not provide an indication of the order, use a second set of rules to verify that the results correspond to a valid ordering of events according to the memory consistency model.

18. The computer readable storage medium as recited in claim 17 , wherein the instructions are further executable to utilize transactional memory axioms to verify the memory consistency model.

19. The computer readable storage medium as recited in claim 18 , wherein said transactional memory axioms are selected from a group consisting of: a program order within a transaction implies global order; memory bafflers are implicit around each transaction; and no other memory operations can intervene between two consecutive operations in a transaction.

20. The computer readable storage medium as recited in claim 16 , wherein the instructions are further executable to:

if the test platform does not provide an indication of an ordering of events, use a heuristic based on a possible write order at each shared memory location of a plurality of shared memory locations to determine whether a result of execution corresponds to a valid ordering of events according to the memory consistency model.