IP Library Granted Patent US 7,785,924
Granted Patent B2
US 7,785,924 · App. 11/751,692 · Granted Aug 31, 2010

Method for making semiconductor chips having coated portions

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Quick Facts
Patent No.
US 7,785,924
App. No.
11/751,692
Granted
Aug 31, 2010
Kind
B2
Abstract

A method for making semiconductor chips having coated portions can include mounting the chips in lead frames, stacking the lead frames in an orientation in which a portion of one lead frame masks a portion of a chip mounted on another lead frame but leaves another portion of the chip mounted on the other lead frame exposed to receive a coating, and depositing a coating on the stacked lead frames using, for example, an evaporative coating machine. In this manner, the coating is deposited on exposed portions of chips, such as its edges, and is not deposited on masked portions of chips, such as bond pads.

Claims (29)

1. A method for making semiconductor chips having coated portions, comprising:

mounting each of a plurality of chips in a plurality of lead frames;

stacking the plurality of lead frames in an orientation in which a portion of one lead frame masks a portion of a chip mounted on another lead frame but leaves another portion of the chip mounted on the other lead frame exposed to receive a coating; and

depositing a coating on the stacked plurality of lead frames in a coating machine in an orientation in which each chip has a surface to be coated oriented at an oblique angle to a coating application direction, the coating substantially simultaneously reaching each lead frame of the stacked plurality of lead frames, whereby the coating is deposited on exposed portions of chips and is not deposited on masked portions of chips.

2. The method claimed in claim 1 , wherein the exposed portions of the chips include edges of edge-emitting laser chips.

3. The method claimed in claim 1 , wherein the masked portions of the chips include bond pads.

4. The method claimed in claim 1 , wherein the step of stacking the plurality of lead frames comprises stacking the lead frames in a stack direction and spatially offsetting each of a plurality of lead frames from another of the plurality of lead frames in a direction perpendicular to the stack direction.

5. The method claimed in claim 1 , wherein:

a plurality of lead frames are mutually connected in a lead frame array, and the step of mounting each of a plurality of chips comprises mounting a chip on each lead frame in the lead frame array.

6. The method claimed in claim 5 , wherein the plurality of lead frames are mutually connected in a strip-like linear lead frame array, and the step of mounting each of a plurality of chips comprises mounting a chip on each lead frame in the strip-like linear lead frame array.

7. The method claimed in claim 1 , wherein a plurality of lead frames are mutually connected in a lead frame array, and the step of stacking the plurality of lead frames comprises stacking one lead frame array on another lead frame array to define a lead frame array stack.

8. The method claimed in claim 7 , wherein each lead frame has a substantially planar shape and wherein:

the step of stacking the plurality of lead frames comprises mounting a lead frame array stack in a coating machine in an orientation with each lead frame lying substantially in a plane oriented at an oblique angle to a coating application direction.

9. The method claimed in claim 7 , wherein the step of stacking the plurality of lead frames comprises arraying a plurality of lead frame array stacks.

10. The method claimed in claim 9 , wherein:

the step of arraying a plurality of stacks of lead frames comprises mounting the plurality of stacks of lead frames in an array in a coating machine; and

the step of depositing a coating on the stacked plurality of lead frames comprises depositing a coating on the arrayed lead frame array stacks in the coating machine.

11. The method claimed in claim 10 , wherein each lead frame includes a mounting portion and a registration portion, the registration portion having at least one feature engageable with a portion of another lead frame to align the stacked lead frames with respect to each other, wherein:

the step of mounting each of a plurality of chips in a plurality of lead frames comprises mounting each chip on a mounting portion of a lead frame; and

the method further comprises the step, following the step of depositing a coating, of separating the mounting portion from the registration portion.

12. A method for making semiconductor chips having coated portions, comprising:

mounting each of a plurality of chips in a plurality of lead frames, wherein a plurality of the lead frames are interconnected to each other to define a lead frame array;

stacking one lead frame array having chips mounted thereon on another lead frame array having chips mounted thereon to define a lead frame array stack, wherein each lead frame is oriented in the lead frame array stack in an orientation in which a portion of each lead frame masks a portion of a chip mounted on another lead frame but leaves another portion of the chip mounted on the other lead frame exposed to receive a coating;

arraying the plurality of lead frame array stacks in a coating machine in an orientation in which each chip has a surface to be coated oriented at an oblique angle to a coating application direction; and

directing a coating material in the coating application direction toward the arrayed lead frame array stacks, whereby the coating is deposited on the surfaces to be coated and is not deposited on masked portions of chips.

13. The method claimed in claim 12 , wherein the step of stacking one lead frame array having chips mounted thereon on another lead frame array having chips mounted thereon comprises spatially offsetting each of a plurality of lead frame arrays from another of the plurality of lead frame arrays.

14. The method claimed in claim 12 , wherein each lead frame includes a mounting portion and a registration portion, the registration portion having at least one feature engageable with a portion of another lead frame to align the stacked lead frames with respect to each other, wherein:

the step of mounting each of a plurality of chips in a plurality of lead frames comprises mounting each chip on a mounting portion of a lead frame; and

the method further comprises the step, following the step of depositing a coating, of separating the mounting portion from the registration portion.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →