Semiconductor device having high cooling efficiency and method for manufacturing the same
View Patent ↗A semiconductor device includes a substrate, a semiconductor chip flip-chip mounted on the substrate, a sealing resin layer sealing the surroundings of the semiconductor chip, and a heat sink bonded to the sealing resin layer through a TIM layer. In addition, a cooling medium is encapsulated in an enclosed space formed on the rear surface of the semiconductor chip.
1. A semiconductor device comprising:
a substrate;
a semiconductor chip which is mounted on the substrate with a front surface of the semiconductor chip facing downward;
a sealing resin layer which seals the semiconductor chip;
a cooling member which is bonded to an upper surface of the sealing resin layer;
a cavity enclosed by at least a lower surface of the cooling member and a rear surface of the semiconductor chip which is exposed on the sealing resin layer; and
a liquid cooling medium which is encapsulated in the cavity, wherein
the rear surface of the semiconductor chip is positioned lower than an uppermost surface of the sealing resin layer and wherein at least a part of the upper surface of the sealing resin layer is inclined toward the rear surface of the semiconductor chip, and
an upper surface of the liquid cooling medium is positioned lower than a level of the uppermost surface of the sealing resin layer when the semiconductor device is horizontally placed.
2. The semiconductor device according to claim 1 , further comprising a thermal interface material layer which bonds the sealing resin layer to the cooling member and is provided on the upper surface of the sealing resin layer.
3. The semiconductor device according to claim 1 , wherein water serving as the liquid cooling medium is encapsulated in the cavity.
4. The semiconductor device according to claim 1 , wherein the internal pressure of the cavity is lower than atmospheric pressure when the semiconductor device is not operated.
5. The semiconductor device according to claim 1 , wherein at least one of the rear surface of the semiconductor chip and a portion of the lower surface of the cooling member, each of which is included in an inner wall of the cavity, is subjected to surface modification.
6. The semiconductor device according to claim 1 , wherein at least one of the rear surface of the semiconductor chip and a portion of the lower surface of the cooling member, each of which is included in an inner wall of the cavity, is subjected to porous plating processing.
7. A semiconductor device comprising:
a substrate;
a semiconductor chip which is mounted on the substrate with a front surface of the semiconductor chip facing downward;
a sealing resin layer which seals the semiconductor chip;
a cooling member which is bonded to an upper surface of the sealing resin layer;
a cavity enclosed by at least a lower surface of the cooling member and a rear surface of the semiconductor chip which is exposed on the sealing resin layer; and
a liquid cooling medium which is encapsulated in the cavity, wherein a bottom surface of the cavity includes the rear surface of the semiconductor chip and a part of the upper surface of the sealing resin layer which is located around the rear surface of the semiconductor chip.