Electrostatic discharge protection structures with reduced latch-up risks
View Patent ↗The present invention provides an ESD protection circuitry in a semiconductor integrated circuit (IC) having protected circuitry to prevent false triggering of the ESD clamp. The circuitry includes an SCR as an ESD clamp having an anode adapted for coupling to a first voltage source, and a cathode adapted for coupling to a second voltage source. The circuitry also includes at least one noise current buffer (NCB) coupled between at least one of a first trigger tap of the SCR and the first voltage source such that the first trigger tap of the SCR is coupled to a power supply.
1. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, the ESD protection circuit comprising:
a first voltage source of a protected circuit node of the IC;
a silicon control rectifier (SCR) having an anode adapted for coupling to the first voltage source, and a cathode adapted for coupling to a second voltage source; and
at least one noise current buffer (NCB) coupled between at least one of a first trigger tap of the SCR and the first voltage source, said at least one of the first trigger tap of the SCR is coupled to a third voltage source.
2. The ESD protection circuit of claim 1 wherein said NCB functions to prevent triggering of the SCR during normal operation.
3. The ESD protection circuit of claim 1 wherein said NCB is a resistor.
4. The ESD protection circuit of claim 1 wherein said NCB is a MOS transistor.
5. The ESD protection circuit of claim 1 wherein said third voltage source is a power supply.
6. The ESD protection circuit of claim 1 wherein said second voltage source is a ground.
7. The ESD protection circuit of claim 1 further comprising a leakage buffer (LB) coupled between the NCB and the third voltage source.
8. The ESD protection circuit of claim 7 wherein said LB functions to prevent the current flow between the first voltage source and the third voltage source during normal operation.
9. The ESD protection circuit of claim 7 wherein said LB is coupled in series between the at least one of the first trigger tap of the SCR and the third voltage source.
10. The ESD protection circuit of claim 7 wherein said LB is coupled between NCB and first trigger tap of the SCR in parallel with said at least one of the first trigger tap of the SCR and the first voltage source.
11. The ESD protection circuit of claim 7 wherein said LB is a diode.
12. The ESD protection circuit of claim 11 wherein said diode is coupled in reverse from third voltage source and the NCB.
13. The ESD protection circuit of claim 1 further comprising a noise current margin increaser (NCMI) coupled in series with said at least one of the first trigger tap of the SCR and the third voltage source.
14. The ESD protection circuit of claim 13 wherein said NCMI functions to increase the voltage design space of the NCB.
15. The ESD protection circuit of claim 13 wherein said NCB is coupled in parallel with the NCMI.
16. The ESD protection circuit of claim 13 wherein said NCMI is a diode.
17. The ESD protection circuit of claim 1 further comprising a noise voltage buffer (NVB) coupled between said at least one of the first trigger tap of the SCR and the third voltage source.