Peripheral devices using phase-change memory

1. A phase-change-memory peripheral comprising:

a peripheral phase-change-memory controller having a central processing unit (CPU) for executing instructions and a random-access memory (RAM) for storing instructions for execution by the CPU;

a bus transceiver in the peripheral phase-change-memory controller for receiving peripheral commands and data from a host over a host bus;

a phase-change-memory controller in the peripheral phase-change-memory controller;

a plurality of phase-change memory (PCM) cells organized as phase-change-memory mass storage devices, coupled to the phase-change-memory controller, for storing non-volatile data for the host, the data in the phase-change-memory mass storage devices being block-addressable and not randomly-addressable;

wherein each PCM cell in the plurality of PCM cells has a first logical state having an alloy in a crystalline phase and a second logical state having the alloy in an amorphous phase, wherein a resistance of the alloy is higher when in the amorphous phase than when in the crystalline phase;

a phase-change-memory bus having data lines for transferring data from the phase-change-memory controller to the phase-change-memory mass storage devices;

wherein instructions are stored only in the RAM for execution, wherein the CPU executes instructions stored only in the RAM;

wherein the instructions are transferred from a copy of the instructions in the phase-change-memory mass storage devices to the RAM during a power-on sequence before the CPU; and

a direct-memory access (DMA) engine for transferring data among the phase-change-memory controller, the RAM, and the bus transceiver, the DMA engine being programmed for a transfer,

whereby instructions are transferred from the phase-change-memory mass storage devices to the RAM for execution by the CPU and whereby the peripheral phase-change-memory controller controls the phase-change-memory mass storage devices that are block-addressable.

2. The phase-change-memory peripheral of claim 1 wherein a PCM cell in the plurality of PCM cells comprises:

a select transistor receiving a word line on a gate, and having a channel between a bit line and a cell node;

an alloy resistor formed from the alloy, coupled between the cell node and an array voltage;

wherein the PCM cell has the first logical state when the alloy resistor has the alloy in the crystalline phase, the alloy resistor having a low resistance that increases a sensing current from the bit line through the select transistor;

wherein the PCM cell has the second logical state when the alloy resistor has the alloy in the amorphous phase, the alloy resistor having a high resistance that reduces the sensing current from the bit line through the select transistor;

wherein the high resistance is larger than the low resistance;

whereby the sensing current is altered by the alloy being in the crystalline phase and the amorphous phase.

3. The phase-change-memory peripheral of claim 2 further comprising write drivers which comprise:

a set current generator, coupled to the bit line, for driving a set current through the select transistor and through the alloy resistor for a set period of time to write the PCM cell into the first logical state in response to set data bits in the data;

a reset current generator, coupled to the bit line, for driving a reset current through the select transistor and through the alloy resistor for a reset period of time to write the PCM cell into the second logical state in response to reset data bits in the data;

a reset timer for determining the reset period of time; and

a set timer for determining the set period of time;

wherein the set period of time is at least double the reset period of time,

whereby the PCM cell is set for a longer time period, and reset for a shorter time period.

4. The phase-change-memory peripheral of claim 3 wherein the reset current is at least twice the set current, and wherein the set current is at least twice the sensing current;

whereby the PCM cell is set by a lower current for a longer time period, and reset by a higher current and a shorter time period.

5. The phase-change-memory peripheral of claim 4 wherein the alloy is a chalcogenide glass layer having a melting point that is higher than a crystallization point.

6. The phase-change-memory peripheral of claim 5 wherein the alloy is an alloy of germanium (Ge), antimony (Sb), and tellurium (Te).

7. The phase-change-memory peripheral of claim 2 wherein a physical address is a partial address of a page of data in the phase-change-memory mass storage devices, the partial address having fewer address bits than a full word address that uniquely identifies a word of data in the phase-change-memory mass storage devices that can be transferred over the data lines in a single bus cycle.

8. The phase-change-memory peripheral of claim 2 further comprising:

an internal bus in the peripheral phase-change-memory controller, the internal bus connecting to the CPU, to the RAM, to a buffer for the bus transceiver, and to the phase-change-memory controller;

wherein the instructions executed by the CPU are transferred from the phase-change-memory mass storage devices over the phase-change-memory bus to the phase-change-memory controller and then to the internal bus for storage by the RAM.

9. The phase-change-memory peripheral of claim 2 wherein the bus transceiver connects to the host bus which is a Multi-Media Card/Secure Digital (MMC/SD) bus, an integrated device electronics (IDE) bus, an AT-Attachment (ATA) bus, a CompactFlash (CF) bus, a Memory Stick (MS) interface bus, a Serial AT-Attachment (SATA) bus, a Small Computer System Interface (SCSI) bus, a PCI-Express (PCIe) interface bus, or a Universal Serial Bus (USB) interface bus.

10. The phase-change-memory peripheral of claim 1 further comprising:

a phase-change-memory programming engine, coupled to the phase-change-memory controller, for programming the DMA engine to transfer instructions from a first page of the phase-change-memory mass storage devices to the RAM during an initial portion of the power-on sequence,

whereby the first page of the phase-change memory mass storage devices is auto-loaded at power-on.

11. The phase-change-memory peripheral of claim 10 wherein the instructions transferred from the first page of the phase-change-memory mass storage devices comprise a boot loader program;

wherein the CPU is brought out of reset and begins executing instructions from the RAM once the boot loader program has been transferred to the RAM by the DMA engine;

wherein the CPU executes the boot loader program loaded into the RAM from the phase-change-memory mass storage devices.

12. A phase-change-memory drive comprising:

host interface means for connecting to a host over a host bus;

a phase-change-memory controller having a processor for executing instructions;

a main memory coupled to the processor for storing instructions for execution by the processor;

phase-change memory means for storing a data word as binary bits each represented by a chalcogenide glass layer having a melting point that is higher than a crystallization point, the chalcogenide glass layer forming a variable resistor that alters a sensing current when a binary bit is read;

wherein a crystalline state of the variable resistor represents a first binary logic state and an amorphous state of the variable resistor represents a second binary logic state for binary bits stored in the phase-change memory means;

phase-change-memory controller means for controlling access of the phase-change memory means;

address translation means for translating block addresses from the processor to access the phase-change memory means as data blocks having multiple data words; and

direct-memory access (DMA) engine means for directly transferring data and instructions over an internal bus among the host interface, the main memory, the processor, and the phase-change-memory controller means,

whereby data blocks are accessed in the phase-change memory means.

13. The phase-change-memory drive of claim 12 further comprising:

phase-change-memory programming engine means for initially programming the DMA engine means to read an initial program from a first page of the phase-change memory means and to write the initial program to the main memory for execution by the processor.

14. The phase-change-memory drive of claim 13 wherein the host interface comprises:

host transceiver means for receiving clocked data and commands from the host bus, and for driving data onto the host bus in response to a command;

host operating register means for storing data and commands in a format specified by a host protocol specification; and

command decoder and validator means, coupled to the host operating register means, for decoding and validating a command received over the host bus by the host transceiver means.

15. The phase-change-memory drive of claim 14 wherein the host bus is a Multi-Media Card/Secure Digital (MMC/SD) bus, an integrated device electronics (IDE) bus, an AT-Attachment (ATA) bus, a CompactFlash (CF) bus, a Memory Stick (MS) interface bus, a Serial AT-Attachment (SATA) bus, a Small Computer System Interface (SCSI) bus, a PCI-Express (PCIe) interface bus, or a Universal Serial Bus (USB) interface bus.

16. The phase-change-memory drive of claim 14 wherein the phase-change memory means further comprises:

an alloy resistor in each memory cell in each array of memory cells, the alloy resistor storing binary data as solid phases each having a different resistivity;

wherein the alloy resistor changes from a crystalline state to an amorphous state when a memory cell is written from a logic 1 state to a logic 0 state in response to a reset current for a reset period of time;

wherein the alloy resistor changes from the amorphous state to the crystalline state when the memory cell is written from a logic 0 state to a logic 1 state in response to a set current for a set period of time;

wherein the amorphous state has a higher resistance than the crystalline state that is sensed by a sense amplifier.

17. The phase-change-memory drive of claim 16 wherein the phase-change-memory controller means further comprises:

a first channel for connecting to a first section of the phase-change memory means, the first channel comprising:

first PCM interface control registers for storing control information for controlling operation of the first section of the phase-change memory means;

first sector buffers for storing a first block of data for writing to the first section of the phase-change memory means;

first PCM DMA engine means for transferring the first block of data from the first sector buffers to the first section of the phase-change memory means;

a second channel for connecting to a second section of the phase-change memory means, the second channel comprising:

second PCM interface control registers for storing control information for controlling operation of the second section of the phase-change memory means;

second sector buffers for storing a second block of data for writing to the second section of the phase-change memory means; and

second PCM DMA engine means for transferring the second block of data from the second sector buffers to the second section of the phase-change memory means,

whereby the phase-change-memory controller means has multiple channels to access the phase-change memory means.

18. A phase-change-memory peripheral system comprising:

a clocked-data interface to a host bus that connects to a host;

a bus transceiver for detecting and processing commands sent over the host bus;

a buffer for storing data sent over the host bus;

an internal bus coupled to the buffer;

a random-access memory (RAM) for storing instructions for execution, the RAM on the internal bus;

a central processing unit, on the internal bus, the CPU accessing and executing instructions in the RAM;

a phase-change-memory controller, on the internal bus, for generating phase-change-memory-control signals and for buffering data to a phase-change-memory bus;

phase-change-memory mass storage devices coupled to the phase-change-memory controller by the phase-change-memory bus, and controlled by the phase-change-memory-control signals;

a direct-memory access (DMA) engine, on the internal bus, for transferring data over the internal bus;

wherein the phase-change-memory mass storage devices comprise an array of memory cells;

an alloy resistor in each memory cell in the array of memory cells, the alloy resistor storing binary data as solid phases each having a different resistivity;

wherein the alloy resistor changes from a crystalline state to an amorphous state when a memory cell is written from a logic 1 state to a logic 0 state in response to a reset current for a reset period of time;

wherein the alloy resistor changes from the amorphous state to the crystalline state when the memory cell is written from a logic 0 state to a logic 1 state in response to a set current for a set period of time;

wherein the amorphous state has a higher resistance than the crystalline state that is sensed by a sense amplifier; and

a plurality of write drivers that apply the set current for the set period of time to memory cells being written by bits in the logic 1 state, and apply the reset current for the reset period of time to memory cells being written by bits in the logic 0 state,

whereby data from the host is stored by the crystalline state and the amorphous state of the alloy resistor in each memory cell.