IP Library Granted Patent US 7,920,893
Granted Patent B2
US 7,920,893 · App. 11/754,407 · Granted Apr 5, 2011

Method and system for transmission or reception of FM signals utilizing a DDFS clocked by an RFID PLL

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Quick Facts
Patent No.
US 7,920,893
App. No.
11/754,407
Granted
Apr 5, 2011
Kind
B2
Abstract

Aspects of a method and system for transmission or reception of FM signals utilizing a DDFS clocked by an RFID PLL are provided. In this regard, one or more signals utilized to transmit or receive FM communication may be generated by clocking a DDFS via a signal generated to enable RFID communication. The DDFS may be controlled via a control word from a processor. In this regard, the control word may determine a frequency and/or phase of the signals output by the DDFS. The control word may be switched between two or more values to generate different frequencies and/or phases in different time intervals. Additionally, the control word may be adjusted to maintain a constant phase and/or frequency in spite of changes to the signal clocking the DDFS.

Claims (30)

1. A method for signal processing, the method comprising:

generating a first signal to enable transmission and reception of radio frequency identification (RFID) signals via a single antenna; and

clocking a direct digital frequency synthesizer (DDFS) via said generated first signal to generate a plurality of signals, wherein:

for transmission via said single antenna, said plurality of generated signals are modulated by audio information to generate a frequency modulated (FM) signal;

for reception via said single antenna, said plurality of generated signals are utilized to demodulate an FM signal modulated by audio information; and

a control word input to said DDFS is switched between two values to simulate said transmission and said reception occurring simultaneously.

2. The method according to claim 1 , comprising generating a control word input to said DDFS that controls a frequency of said plurality of signals generated by said DDFS.

3. The method according to claim 1 , comprising switching said control word input to said DDFS between two values in successive time intervals to perform time-division duplexing of FM transmission and FM reception.

4. The method according to claim 3 , wherein said FM transmission occurs at a first frequency and said FM reception occurs at a second frequency.

5. The method according to claim 1 , comprising adjusting a control word input to said DDFS, which controls a frequency of said plurality of signals generated by said DDFS, in response to changes in a frequency of said first signal.

6. The method according to claim 1 , wherein a frequency of said first signal is within one of the following frequency bands: 868 MHz to 928 MHz, 2.4 GHz to 2.483 GHz, and 5.725 to 5.875 GHz.

7. The method according to claim 1 , wherein a frequency of each of said generated plurality of signals is within a frequency band of 60 MHz to 130 MHz.

8. The method according to claim 1 , wherein each of said generated plurality of signals comprise an in-phase component and a quadrature-phase component.

9. The method according to claim 1 , comprising generating said first signal via a phase locked loop.

10. The method according to claim 9 , wherein said phase locked loop operates at a fixed frequency.

11. A system for signal processing, the system comprising:

one or more circuits that generate a first signal to enable transmission and reception of radio frequency identification (RFID) signals via a single antenna; and

said one or more circuits clocks a direct digital frequency synthesizer (DDFS) via said generated first signal to generate a plurality of signals, wherein:

for transmission via said single antenna, said a plurality of generated signals is modulated by audio information to generate a frequency modulated (FM) signal; or

for reception via said single antenna, said a plurality of generated signals are utilized to demodulate an FM signal modulated by audio information; and

a control word input to said DDFS is switched between two values to simulate said transmission and said reception occurring simultaneously.

12. The system according to claim 11 , wherein said one or more circuits generate a control word input to said DDFS that controls a frequency of said a plurality of signals generated by said DDFS.

13. The system according to claim 10 , wherein said one or more circuits switches said control word input to said DDFS between two values in successive time intervals to perform time-division duplexing of FM transmission and FM reception.

14. The system according to claim 13 , wherein said FM transmission occurs at a first frequency and said FM reception occurs at a second frequency.

15. The system according to claim 11 , wherein said one or more circuits adjusts a control word input to said DDFS, which controls a frequency of said a plurality of signals generated by said DDFS, in response to changes in a frequency of said first signal.

16. The system according to claim 11 , wherein a frequency of said first signal is within one of the following frequency bands: 868 MHz to 928 MHz, 2.4 GHz to 2.483 GHz, and 5.725 to 5.875 GHz.

17. The system according to claim 11 , wherein a frequency of each of said generated a plurality of signals is within a frequency band of 60 MHz to 130 MHz.

18. The system according to claim 11 , wherein each of said generated a plurality of signals comprise an in phase component and a quadrature component.

19. The system according to claim 11 , wherein said one or more circuits comprise a phase locked loop that generates said first signal.

20. The system according to claim 19 , wherein said phase locked loop operates at a fixed frequency.

Assignments (8)
MERGER AND CHANGE OF NAME Recorded May 22, 2017
From: FREESCALE SEMICONDUCTOR, INC.; NXP USA, INC.
To: NXP USA, INC.
Reel/Frame 042525/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ADD OMITTED PAGE 6 OF 22 TO THE ASSIGNMENT AGREEMENT PREVIOUSLY RECORDED AT REEL: 040569 FRAME: 0572. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 28, 2017
From: BROADCOM CORPORATION
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 042108/0597 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2016
From: BROADCOM CORPORATION
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040569/0572 →
RELEASE OF SECURITY INTEREST Recorded Sep 30, 2016
From: BANK OF AMERICA N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 040192/0701 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TYPOGRAPHICAL ERROR OF INVENTOR NAME PREVIOUSLY RECORDED ON REEL 019463 FRAME 0711. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT SPELLING OF INVENTOR AHMADREZA ROFOUGARAN. Recorded Aug 21, 2007
From: ROFOUGARAN, AHMADREZA; ROFOUGARAN, MARYAM
To: BROADCOM CORPORATION
Reel/Frame 019726/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2007
From: ROFOUGARAN, ADMADREZA; ROFOUGARAN, MARYAM
To: BROADCOM CORPORATION
Reel/Frame 019463/0711 →