Thin film transistor array panel
View Patent ↗A thin film transistor array panel includes an insulating substrate, a plurality of gate lines formed on the substrate, a plurality of data lines, and an insulating layer. Each of the gate lines include a plurality of gate electrodes. The data lines cross the gate lines with insulation therebetween. Each of the data lines include a plurality of source electrodes. A plurality of drain electrodes face the source electrodes. The insulating layer is formed on the gate lines, the data lines, and the drain electrodes. A plurality of pixel electrodes are formed on the insulating layer and connected to the drain electrodes. The insulating layer has an opening or a trench and the opening or the trench is disposed in a part of the insulating layer that is not covered by the pixel electrodes.
1. A thin film transistor array panel, comprising:
an insulating substrate;
a plurality of gate lines formed on the substrate, wherein each of the gate lines include a plurality of gate electrodes;
a plurality of data lines disposed on the insulating substrate, wherein each of the data lines include a plurality of source electrodes;
a plurality of drain electrodes facing the source electrodes;
an insulating layer formed on the gate lines, the data lines, and the drain electrodes, wherein at least a portion of the insulating layer is removed to have an opening or a trench and the opening or trench is disposed between adjacent pixel electrodes;
a plurality of pixel electrodes formed on the insulating layer and connected to the drain electrodes; and
a light blocking layer disposed between adjacent pixel electrodes and overlapping the opening or the trench.
2. The thin film transistor array panel of claim 1 , wherein the insulating layer is made of an organic insulating material.
3. The thin film transistor array panel of claim 1 , wherein the light blocking layer is made of a same layer as the gate lines without overlapping the gate lines.
4. The thin film transistor array panel of claim 3 , wherein the light blocking layer overlaps the data lines.
5. The thin film transistor array panel of claim 1 , further comprising a passivation layer formed under the insulating layer and covering the gate lines, the data lines, and the drain electrodes.
6. The thin film transistor array panel of claim 5 , wherein the passivation layer and the insulating layer have a plurality of contact holes to connect the pixel electrodes to the drain electrodes.
7. The thin film transistor array panel of claim 1 , wherein the pixel electrodes include a transparent electrode made of a transparent conductive material and a reflective electrode made of a reflective material.
8. The thin film transistor array panel of claim 7 , wherein the insulating layer has an embossed surface.
9. The thin film transistor array panel of claim 8 , wherein a pixel region occupied by a pixel electrode includes a first region only occupied by the transparent electrode and a second region occupied by the transparent electrode and the reflective electrode.
10. The thin film transistor array panel of claim 1 , wherein the respective adjacent pixel electrodes extend to opposing side walls of the opening or the trench.
11. A thin film transistor array panel, comprising:
an insulating substrate;
a plurality of gate lines formed on the substrate, wherein each of the gate lines include a plurality of gate electrodes;
a plurality of data lines disposed on the insulating substrate, wherein each of the data lines include a plurality of source electrodes;
a plurality of drain electrodes facing the source electrodes;
an insulating layer formed on the gate lines, the data lines, and the drain electrodes;
a plurality of pixel electrodes formed on the insulating layer and connected to the drain electrodes; and
a light blocking layer disposed between adjacent pixel electrodes,
wherein the insulating layer has a trench and the trench is overlapped and disposed within a boundary of the light blocking layer.
12. The thin film transistor array panel of claim 11 , wherein the insulating layer is made of an organic insulating material.
13. The thin film transistor array panel of claim 11 , wherein the light blocking layer overlaps the data lines.
14. The thin film transistor array panel of claim 11 , further comprising a passivation layer formed under the insulating layer and covering the gate lines, the data lines, and the drain electrodes.
15. The thin film transistor array panel of claim 14 , wherein the passivation layer and the insulating layer have a plurality of contact holes to connect the pixel electrodes to the drain electrodes.
16. The thin film transistor array panel of claim 11 , wherein the pixel electrodes include a transparent electrode made of a transparent conductive material and a reflective electrode made of a reflective material.
17. The thin film transistor array panel of claim 16 , wherein the insulating layer has an embossed surface.
18. The thin film transistor array panel of claim 17 , wherein a pixel region occupied by a pixel electrode includes a first region only occupied by the transparent electrode and a second region occupied by the transparent electrode and the reflective electrode.