Validating apparatus for use with a pair of integrated circuits
View Patent ↗An apparatus is provided for validating a device. The apparatus includes a first integrated circuit which is configured to generate a random number, reference information using the random number and a secret key. A control system is configured to: receive the random number and the reference information from the first integrated circuit, receive validation information from a second integrated circuit positioned on the device whereby the validation information is generated by the second integrated circuit using the random number and the secret key, and compare the reference and validation information received from the integrated circuits to validate the device.
1. An apparatus for validating a printing consumable device, the apparatus comprising:
a first integrated circuit which generates a random number, reference information using the random number and a secret key; and
a printer which receives the random number and the reference information from the first integrated circuit, receives validation information from a second integrated circuit positioned on the printing consumable device whereby the validation information is generated by the second integrated circuit using the random number and the secret key, and compares the reference and validation information received from the integrated circuits to validate the printing consumable device for use with the printer.
2. An apparatus as claimed in claim 1 , wherein the reference information is generated by applying a function to the generated random number based upon the secret key.
3. An apparatus as claimed in claim 2 , wherein the function is a digital signature function or a one-way function.
4. An apparatus as claimed in claim 1 , wherein the validation information is generated by applying a function to the random number based upon the secret key.
5. An apparatus as claimed in claim 4 , wherein the function is a digital signature function.
6. An apparatus as claimed in claim 5 , wherein the digital signature function is a symmetric cryptographic function.
7. An apparatus as claimed in claim 1 , wherein the first integrated circuit generates a vector of random numbers and is configured select the next consecutive random number in the vector with each successive validation attempt.