IP Library Granted Patent US 7,961,782
Granted Patent B2
US 7,961,782 · App. 11/757,882 · Granted Jun 14, 2011

Interference suppression processing unit and a method of suppressing interference in wireless data communication

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Quick Facts
Patent No.
US 7,961,782
App. No.
11/757,882
Granted
Jun 14, 2011
Kind
B2
Abstract

The interference suppression processing unit includes N a ≧1 receiver paths to transmit respective N a ≧1 received data sequences received from respective N a ≧1 antennas, and a signal generation unit to generate K≧N a signal data sequences from the received data sequences. The interference suppression processing unit also includes K≧N a signal paths that each transmit one of the signal data sequences, a prefilter unit in each one of the signal paths, and a combiner having K≧N a input terminals each one connected to an output terminal of one of the prefilter units.

Claims (92)

1. An interference suppression processing unit, comprising:

N a ≧2 receiver paths configured to transmit respective N a ≧2 received data sequences received from respective N a ≧2 antennas;

a signal generation unit configured to generate K>N a signal data sequences from the received data sequences;

K>N a signal paths each configured to transmit one of the respective signal data sequences;

a plurality of prefilter units, each coupled to one of the signal paths; and

a combiner comprising K>N a input terminals that are each connected to an output terminal of one of the prefilter units,

wherein the signal generation unit is configured to generate K 1 first signal data sequences, wherein each first signal data sequence is identical to one of the received data sequences, respectively, and K 2 second signal data sequences, wherein each second signal data sequence is not identical to any one of the received data sequences, respectively, and wherein K 1 +K 2 =K.

2. The processing unit of claim 1 , wherein the K 2 signal data sequences are each comprised of one of the following:

a real part of one of the received data sequences;

an imaginary part of one of the received data sequences;

one of polyphases of one of the received data sequences;

a real part of one of the polyphases of one of the received data sequences; and

an imaginary part of one of the polyphases of one of the received data sequences.

3. The processing unit of claim 2 , wherein the signal generation unit is configured to determine the one of the polyphases by determining the polyphase that yields the lowest sampling timing error.

4. The processing unit of claim 1 , wherein each prefilter unit comprises a linear, finite-impulse-response filter.

5. The processing unit of claim 1 , wherein the signal generation unit is configured such that K is a fixed value.

6. An interference suppression and equalization processing apparatus, comprising:

an interference suppression processing unit comprising N a ≧2 receiver paths configured to receive respective N a ≧2 received data sequences received from respective N a ≧2 antennas, a signal generation unit configured to generate K>N a signal data sequences from the received data sequences, K>N a signal paths configured to transmit each one of the signal data sequences, a plurality of prefilter units, each coupled to one of the signal paths, a first combiner comprising K>N a input terminals each one connected to an output terminal of one of the prefilter units, and an output terminal; and

an equalization processing unit, comprising an input terminal connected to the output terminal of the first combiner, a slicer unit, and an output terminal coupled to the output of the slicer unit,

wherein the signal generation unit is configured to generate K 1 first signal data sequences, wherein each first signal data sequence is identical to one of the received data sequences, respectively, and K 2 second signal data sequences, wherein each second signal data sequence is not identical to any one of the received data sequences, respectively, and wherein K 1 +K 2 =K.

7. The processing apparatus of claim 6 , wherein the equalization processing unit comprises:

a second combiner comprising a first input terminal connected to the output terminal of the first combiner, and an output terminal;

the slicer unit comprising an input terminal connected to the output terminal of the second combiner; and

a feedback filter unit comprising an input terminal connected to the output terminal of the slicer unit, and an output terminal connected to a second input terminal of the second combiner, wherein the sign of an output signal of the feedback filter unit is changed when the output signal thereof is delivered to the second combiner.

8. The processing apparatus of claim 7 , wherein the feedback filter unit comprises a linear, finite-impulse-response filter.

9. The processing apparatus of claim 7 , further comprising:

a third combiner comprising a first input terminal connected to the output terminal of the second combiner, a second input terminal comprising an input for a training sequence, and an output terminal, wherein the sign of the output signal of the second combiner is changed when the output signal is delivered to the third combiner.

10. The processing apparatus of claim 9 , further comprising:

a data processing unit comprising an input terminal connected to the output terminal of the third combiner, and K output terminals, wherein each output terminal is connected to a respective input terminal of one of the prefilter units.

11. The processing apparatus of claim 6 , wherein the second signal data sequences are each comprised of one of the following:

a real part of one of the received data sequences;

an imaginary part of one of the received data sequences;

one of polyphases of one of the received data sequences;

a real part of one of the polyphases of one of the received data sequences; and

an imaginary part of one of the polyphases of one of the received data sequences.

12. The processing apparatus of claim 11 , wherein the signal generation unit is configured to determine the one of the polyphases by determining the polyphase that yields the lowest sampling timing error.

13. The processing apparatus of claim 6 , wherein each prefilter unit comprises a linear, finite-impulse-response filter.

14. The processing apparatus of claim 6 , wherein the signal generation unit is configured such that K is a fixed value.

15. A method of suppressing interference of a received data signal in wireless data communication, comprising:

receiving N a ≧2 data sequences from respective N a ≧2 antennas;

generating K>N a signal data sequences from the received data sequences;

filtering each one of the signal data sequences with a respective one of a plurality of prefilter units; and

combining the filtered signal data sequences in a first combiner,

wherein generating K>N a signal data sequences comprises:

providing K 1 first signal data sequences, wherein each first signal data sequence is identical to one of the received data sequences, respectively, and

generating K 2 second signal data sequences, wherein each second signal data sequence is not identical to any one of the received data sequences, respectively, wherein K 1 +K 2 =K.

16. The method of claim 15 , further comprising:

receiving a training sequence of known training symbols at the N a ≧2 antennas; and

setting coefficients of the prefilter units such that an error signal is minimized, wherein the error signal is obtained from a difference between the training sequence and a signal derived from an output signal of the first combiner.

17. The method of claim 16 , further comprising:

supplying the output signal of the first combiner to a first input of a second combiner;

supplying an output signal of the second combiner to a slicer;

supplying an output signal of the slicer to a feedback filter unit; and

supplying an output signal of the feedback filter unit to a second input of the second combiner, wherein the error signal is based on a difference signal between the training sequence and the output signal of the second combiner.

18. The method of claim 17 , further comprising:

setting coefficients of the prefilter units and the feedback filter unit such that the error signal is minimized.

19. The method of claim 17 , wherein the error signal comprises a mean square error between the training sequence and the output signal of the second combiner.

20. The method of claim 15 , wherein the K 2 signal data sequences are each comprised of one of the following:

a real part of one of the received data sequences;

an imaginary part of one of the received data sequences;

one of the polyphases of one of the received data sequences;

a real part of one of the polyphases of one of the received data sequences; and

an imaginary part of one of the polyphases of one of the received data sequences.

21. The method of claim 20 , further comprising:

determining the one of the polyphases by determining the polyphase that yields the lowest sampling timing error.

22. A method of suppressing interference of a received data signal and equalizing the received data signal in wireless data communication, comprising:

receiving N a ≧2 data sequences from respective N a ≧2 antennas;

generating K>N a signal data sequences from the received data sequences;

filtering each one of the signal data sequences with a respective one of a plurality of prefilter units;

combining the filtered signal data sequences in a first combiner; and

equalizing an output signal of the first combiner,

wherein generating K>N a signal data sequences comprises:

providing K 1 first signal data sequences, wherein each first signal data sequence is identical to one of the received data sequences, respectively, and

generating K 2 second signal data sequences, wherein each second signal data sequence is not identical to any one of the received data sequences, respectively, wherein K 1 +K 2 =K.

23. The method of claim 22 , further comprising:

receiving a training sequence of known training symbols at the N a ≧2 antennas; and

setting coefficients of the prefilter units such that an error signal is minimized, wherein the error signal is obtained from the training sequence and a signal derived from an output signal of the first combiner.

24. The method of claim 23 , wherein equalizing the output signal of the first combiner comprises:

supplying the output signal of the first combiner to a first input of a second combiner;

supplying an output signal of the second combiner to a slicer;

supplying an output signal of the slicer to a feedback filter unit; and

supplying an output signal of the feedback filter unit to a second input of the second combiner, wherein the error signal is based on a difference signal between the training sequence and the output signal of the second combiner.

25. The method of claim 24 , further comprising setting coefficients of the prefilter units and the feedback filter unit such that the error signal is minimized.

26. The method of claim 24 , wherein the error signal comprises a mean square error between the training sequence and the output signal of the second combiner.

27. The method of claim 22 , wherein the second signal data sequences are each comprised of one of the following:

a real part of one of the received data sequences;

an imaginary part of one of the received data sequences;

one of polyphases of one of the received data sequences;

a real part of one of the polyphases of one of the received data sequences; and

an imaginary part of one of the polyphases of one of the received data sequences.

28. The method of claim 27 , further comprising:

determining the one of the polyphases by determining the polyphase that yields the lowest sampling timing error.

Assignments (6)
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2012
From: INFINEON TECHNOLOGIES DELTA GMBH
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027531/0108 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE TO 09/30/2009 PREVIOUSLY RECORDED ON REEL 026685 FRAME 0165. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2011
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES DELTA GMBH
Reel/Frame 026908/0766 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2011
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES DELTA GMBH
Reel/Frame 026685/0165 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2007
From: WU, XIAOFENG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 019749/0176 →