Pin multiplexing
View Patent ↗A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.
1. A semiconductor device coupled to input/output pins, the semiconductor device comprising:
a first core to operate a first function;
a second core to operate a second function;
a multiplexer arranged to set the input/output pins according to the first function or to the second function;
an arbiter arranged to receive requests from the first and second cores to use the input/output pins and to grant use of the input/output pins to a selected core; and
a register arranged to store a delay value indicative of one of a plurality of delay settings to be applied by the arbiter when granting use of the input/output pins to the second core, wherein each of the plurality of delay settings comprises a different number of clock cycle delays.
2. The semiconductor device of claim 1 , wherein the register comprises a programmable register.
3. The semiconductor device of claim 2 , further comprising a control unit configured to program the register.
4. The semiconductor device of claim 3 , wherein the control unit is configured to program the register dependent on a type of external device operated by the first core.
5. The semiconductor device of claim 3 , wherein the first core is associated with an interface through which the control unit accesses the register.
6. The semiconductor device of claim 1 , wherein the arbiter is further arranged to receive an access status from the first core indicating whether or not the first core progresses an external access via the input/output pins.
7. The semiconductor device of claim 6 , wherein the arbiter is arranged to apply the one of the plurality of delay settings in between a time when it receives the access status from the first core indicating that access has been completed and a time when it grants use of the input/output pins to the second core.
8. The semiconductor device of claim 1 , wherein the first core is configured to support a plurality of external devices with different access speeds.
9. The semiconductor device of claim 1 , wherein the first core is configured to support one or more external devices of flash memory type.
10. The semiconductor device of claim 9 , wherein the second core is configured to support a synchronous dynamic random access memory as an external device.
11. The semiconductor device of claim 10 , wherein the second core comprises a single data rate interface controller.
12. A method for multiplexing across a plurality of input/output pins between a first core to operate a first function and a second core to operate a second function, the method comprising:
sending a request signal from the second core to an arbiter for use of the input/output pins;
commanding the first core to stop external access via the input/output pins; and
granting use of the input/output pins to the second core under control of one of a plurality of predetermined delay settings, each predetermined delay setting corresponding to a different number of clock cycle delays.
13. The method of claim 12 , wherein the predetermined delay setting comprises a programmable delay setting.
14. The method of claim 12 , further comprising programming the predetermined delay setting, wherein the delay is dependent on a type of external device operated by the first core.
15. The method of claim 13 , further comprising programming the predetermined delay setting by writing a value indicative of the predetermined delay setting into a register.
16. The method of claim 12 , further comprising sending an access status from the first core, the access status indicating whether or not the first core progresses an external access via the input/output pins to the arbiter.
17. The method of claim 16 , further comprising inserting a clock cycle delay between a time when the arbiter receives the access status from the first core indicating that access has been completed and a time when the arbiter grants use of the input/output pins to the second core.
18. The method of claim 12 , wherein commanding the first core to stop external access comprises the arbiter commanding the first core to stop external access.
19. The method of claim 18 , wherein granting the use of the input/output pins to the second core comprises the arbiter granting use of the input/output pins to the second core.