Reliable message transport network
A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.
1. A method of reliably sending data in a computerized network, comprising:
sending packets comprising part of a message to a receiver;
sending a separate message complete packet to the receiver after sending all packets comprising part of the message, wherein the message complete packet indicates the number of packets in the message;
tracking in the receiver a number of received packets that comprise part of the message by counting in a counter the number of packets received comprising part of the message:
comparing the counted number of received packets comprising part of the message to the number of packets in the message;
maintaining a message buffer entry in the sender comprising the sent packets;
tracking acknowledgment from the receiver that sent packets have been received;
maintaining a timer indicating a time since message data has been sent; and
resending packets not acknowledged upon the timer reaching a timeout state.
2. The method of claim 1 , wherein the timer is a packet timer operable to count the time since a packet has been sent.
3. The method of claim 1 , wherein the timer is a message timer operable to count the time since a message has been processed.
4. The method of claim 1 , wherein resending packets not acknowledged comprises sending the packets using alternate routing.
5. The method of claim 1 , wherein the network is an interprocessor network in a multiprocessor computer system.
6. The method of claim 1 , further comprising receiving the packets in the receiver in an order other than the order sent from the sender.
7. The method of claim 1 , further comprising detecting when all packets have been received in receiver by tracking number of received packets in message.
8. A method of reliably receiving data in a computerized network, comprising receiving packets comprising part of a message from a sender;
receiving a separate message complete packet sent from the sender after sending all packets comprising part of the message, wherein the message complete packet indicates the number of packets in the message;
counting the number of received packets in a counter;
comparing the counted number of received packets comprising part of the message to the number of packets in the message;
sending acknowledgment to the sender that received packets have been received;
tracking packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received by tracking the number of received packets that comprise part of the message; and
processing packets once all packets in a message are received irrespective of the order packets were received to reassemble the received message.
9. The method of claim 8 , wherein one or more of the packets comprise resent packets sent after the packets failed to reach the receiver before a timeout.
10. The method of claim 9 , wherein the resent packets are sent using alternate routing.
11. The method of claim 8 , wherein the network is an interprocessor network in a multiprocessor computer system.
12. The method of claim 8 , further comprising buffering all sent packets in the sender so that sent packets can be resent.
13. A multiprocessor computer system comprising:
a sending processor node operable to send packets comprising part of a message to a receiving processing node, to maintain a message buffer entry in the sending processor node comprising the sent packets, to track acknowledgment from the receiving processing node that sent packets have been received; to maintain a timer indicating the time since message data has been sent, to send a separate message complete packet to the receiver after sending all packets comprising part of the message, wherein the message complete packet indicates the number of packets in the message, and to resend packets not acknowledged upon the timer reaching a timeout state; and
a receiving processing node operable to send acknowledgment to the sending processor node that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received by counting the number of received packets that comprise part of the message in a counter and comparing the counted number of received packets comprising part of the message to the number of packets in the message, and to process packets once all packets in a message are received to reassemble the received message.
14. The multiprocessor computer system of claim 13 , wherein the timer is a packet timer operable to count the time since a packet has been sent.
15. The multiprocessor computer system of claim 13 , wherein the timer is a message timer operable to count the time since a message has been processed.
16. The multiprocessor computer system of claim 13 , wherein resending packets not acknowledged comprises sending the packets using alternate routing.
17. The multiprocessor computer system of claim 13 , wherein the network is an interprocessor network in a multiprocessor computer system.
18. The multiprocessor computer system of claim 13 , wherein the packets are received in the receiving processing node in an order other than the order sent from the sending processor node.
19. The multiprocessor computer system of claim 13 , further comprising detecting when all packets have been received in receiver by tracking number of received packets in message.