Large-area nanoenabled macroelectronic substrates and uses therefor
View Patent ↗A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
1. A semiconductor device comprising:
a substrate;
a plurality of nanowires deposited or formed on the substrate, wherein said nanowires each comprise a core made of a first material and at least a first shell layer made of a second material disposed about said core, wherein said second material is made from a high dielectric constant material; and
at least a first source contact and a first drain contact formed in or on the substrate providing electrical connectivity to the plurality of nanowires, wherein the nanowires each form an individual channel between said at least first source and drain contacts.
2. The semiconductor device of claim 1 , further comprising a thin film of nanowires including the plurality of nanowires of claim 1 .
3. The semiconductor device of claim 1 , wherein the plurality of nanowires comprises at least five or more nanowires.
4. The semiconductor device of claim 1 , wherein the plurality of nanowires comprises at least ten or more nanowires.
5. The semiconductor device of claim 1 , wherein the plurality of nanowires are aligned substantially parallel to their long axis.
6. The semiconductor device of claim 1 , further comprising at least one gate contact formed above or below said plurality of nanowires.
7. The semiconductor device of claim 1 , wherein said substrate comprises a flexible thin film.
8. The semiconductor device of claim 1 , wherein said substrate comprises a polymer.
9. The semiconductor device of claim 1 , further comprising a second shell layer disposed about said first shell layer.
10. The semiconductor device of claim 9 , wherein the second shell layer is made from a third material, wherein said third material is compositionally different from said second material.
11. The semiconductor device of claim 10 , wherein said second shell layer comprises highly-doped amorphous silicon to thereby form a gate electrode about said first shell layer.
12. The semiconductor device of claim 1 , wherein said second material of said first shell layer is selected from the group comprising silicon nitride, Ta 2 O 5 , TiO 2 , ZrO 2 , HfO 2 , and Al 2 O 3 .
13. The semiconductor device of claim 12 , wherein said second material of said first shell layer is made from silicon nitride and said first material of said core is made from silicon.
14. The semiconductor device of claim 12 , wherein said second material of said first shell layer is made from HfO 2 and said first material of said core is made from silicon.
15. The semiconductor device of claim 12 , wherein said second material of said first shell layer is made from Al 2 O 3 and said first material of said core is made from silicon.
16. The semiconductor device of claim 12 , wherein said second material of said first shell layer is made from ZrO 2 and said first material of said core is made from silicon.
17. The semiconductor device of claim 12 , wherein said second material of said first shell layer is made from TiO 2 and said first material of said core is made from silicon.
18. The semiconductor device of claim 12 , wherein said second material of said first shell layer is made from Ta 2 O 5 and said first material of said core is made from silicon.