Clock distribution circuit, semiconductor integrated circuit and method of designing clock distribution circuit
View Patent ↗A clock distribution circuit, which is provided in IC that has a first sequential circuit receiving first clock through a first branch node on a first clock network, a second sequential circuit receiving second clock through a second branch node on a second clock network, and a data transfer path between the first and second sequential circuits, includes: a first PLL receiving a first feedback clock that is the first clock branched at the first branch node and outputting the first clock to the first clock network based on the first feedback clock; and a second PLL receiving a second feedback clock that is the second clock branched at the second branch node and outputting the second clock to the second clock network based on the second feedback clock. A branch node is provided at least one of between the first PLL and the first branch node and between the second PLL and the second branch node.
1. A clock distribution circuit in a semiconductor integrated circuit that has a first sequential circuit which operates in accordance with a first clock signal distributed through a first branch node on a first clock distribution network, a second sequential circuit which operates in accordance with a second clock signal distributed through a second branch node on a second clock distribution network, and a data transfer path provided between said first sequential circuit and said second sequential circuit, comprising:
a first PLL circuit configured to receive a first feedback clock signal that is said first clock signal branched at said first branch node, and to output said first clock signal to said first clock distribution network based on said first feedback clock signal and a first reference clock signal; and
a second PLL circuit configured to receive a second feedback clock signal that is said second clock signal branched at said second branch node, and to output said second clock signal to said second clock distribution network based on said second feedback clock signal and a second reference clock signal,
wherein a branch node is provided at least one of between an output of said first PLL circuit and said first branch node on said first clock distribution network and between an output of said second PLL circuit and said second branch node on said second clock distribution network,
wherein said first branch node is closest to said first sequential circuit among a plurality of branch nodes on a first path from said first PLL circuit to said first sequential circuit.
2. The clock distribution circuit according to claim 1 ,
wherein said second branch node is closest to said second sequential circuit among a plurality of branch nodes on a second path from said second PLL circuit to said second sequential circuit.
3. The clock distribution circuit according to claim 1 ,
wherein a reference clock signal input from an outside through a clock input buffer is supplied as said first reference clock signal and said second reference clock signal to said first PLL circuit and said second PLL circuit, respectively.
4. The clock distribution circuit according to claim 1 ,
wherein said first reference clock signal is supplied from an outside to said first PLL circuit through a first clock input buffer, and said second reference clock signal is supplied from an outside to said second PLL circuit through a second clock input buffer.
5. The clock distribution circuit according to claim 1 ,
wherein a delay of said first clock signal from said first branch node to said first sequential circuit is equal to a delay of said first clock signal from said first branch node to said first PLL circuit, and a delay of said second clock signal from said second branch node to said second sequential circuit is equal to a delay of said second clock signal from said second branch node to said second PLL circuit.
6. The clock distribution circuit according to claim 3 , further comprising:
a first buffer provided on a feedback path of said first clock signal from said first branch node to said first PLL circuit, a delay of said first buffer being equal to that of said clock input buffer; and
a second buffer provided on a feedback path of said second clock signal from said second branch node to said second PLL circuit, a delay of said second buffer being equal to that of said clock input buffer.
7. The clock distribution circuit according to claim 4 , further comprising:
a first buffer provided on a feedback path of said first clock signal from said first branch node to said first PLL circuit, a delay of said first buffer being equal to that of said first clock input buffer; and
a second buffer provided on a feedback path of said second clock signal from said second branch node to said second PLL circuit, a delay of said second buffer being equal to that of said second clock input buffer.
8. A semiconductor integrated circuit comprising said clock distribution circuit according to claim 1 .
9. A clock distribution circuit in a semiconductor integrated circuit, the semiconductor integrated circuit comprising:
a first sequential circuit which operates in accordance with a first clock signal distributed through a first branch node on a first clock distribution network;
a second sequential circuit which operates in accordance with a second clock signal distributed through a second branch node on a second clock distribution network; and
a data transfer path provided between said first sequential circuit and said second sequential circuit,
the clock distribution circuit comprising:
a first PLL circuit configured to receive a first feedback clock signal from said first branch node, and to output said first clock signal to said first clock distribution network based on said first feedback clock signal and a first reference clock signal; and
a second PLL circuit configured to receive a second feedback clock signal from said second branch node, and to output said second clock signal to said second clock distribution network based on said second feedback clock signal and a second reference clock signal,
wherein at least a third branch node is provided between an output of said first PLL circuit and said first branch node on said first clock distribution network, and at least a fourth branch node is provided between an output of said second PLL circuit and said second branch node on said second clock distribution network.