Field effect transistor capable of reducing shift of threshold voltage
View Patent ↗A problem is arisen in conventional J-FETs that a shifting in a threshold voltage (V T ) is generated before or after an energization with a gate current. A junction gate field effect transistor (J-FET) according to the present invention includes an undoped InGaAs channel layer 5 , which is capable of accumulating carrier of a first conductivity type, a p + type GaAs layer 17 (semiconductor layer), which is provided on the undoped InGaAs channel layer 5 , and contains an impurity of a second conductivity type, and a gate electrode 18 , which is provided on the p + type GaAs layer 17 . Here, the concentration of hydrogen contained in the p + type GaAs layer 17 is lower than the concentration of the second conductivity type carrier in the p + type GaAs layer 17.
1. A field effect transistor, comprising:
a channel layer, which is capable of accumulating a first conductivity type carrier;
a semiconductor layer, provided on said channel layer and containing a second conductivity type impurity; and
a gate electrode provided on said semiconductor layer,
wherein a concentration of hydrogen contained in said semiconductor layer is lower than a concentration of said second conductivity type carrier in the semiconductor layer, and
wherein said concentration of said second conductivity type impurity is equal to or more than 1×10 20 cm −3 .
2. The field effect transistor as set forth in claim 1 , wherein a relationship of said concentration of hydrogen (dh [cm −3 ]) and said concentration of carrier (dc [cm −3 ])is:
dh≦ 4.4×10 −1 ×dc−1.5×10 19 .
3. The field effect transistor as set forth in claim 1 , wherein said concentration of hydrogen is equal to or lower than 2×10 18 cm −3 .
4. The field effect transistor as set forth in claim 1 , wherein the impurity of said second conductivity type is carbon.