Method and system for monitoring module power status in a communication device
View Patent ↗Methods and systems for monitoring operating status of a device are provided. Aspects of the method may include receiving within a chip, a signal indicative of a power status of an on-chip device. An output signal indicative of the power status may be generated from within the chip, while the chip is operating. The generated output signal may be communicated outside the chip via a serial bus, a plurality of pin connections on said chip, and/or a general purpose input/output connection. The generated output signal may be multiplexed on at least one pin on the chip and it may comprise a clock signal and/or a data signal. The data signal may comprise sequential power status information for a plurality of on-chip devices.
1. A method for monitoring operating status of a plurality of on-chip modules, the method comprising:
receiving, within a chip, a plurality of signals containing power status information regarding the on-chip modules, wherein the signals contain information output from a plurality of resistor drops coupled to the on-chip modules; and
generating, from within the chip, a clock signal and a data signal, wherein a predetermined number of clock cycles of the data signal represent a power status of a specific on-chip module in the plurality of on-chip modules.
2. The method of claim 1 , further comprising:
communicating the clock signal and the data signal outside the chip.
3. The method of claim 1 , further comprising:
communicating the clock signal and the data signal via a serial bus.
4. The method of claim 1 , further comprising:
communicating the clock signal and the data signal via a plurality of pin connections on the chip.
5. The method of claim 2 , further comprising:
communicating the clock signal and the data signal via a general purpose input/output connection.
6. The method of claim 1 , wherein the data signal comprises sequential power status information for the plurality of on-chip modules.
7. The method of claim 1 , further comprising:
after acquiring a first signal indicative of a power status of at least one of the plurality of on-chip modules, acquiring a second signal indicative of the power status of the at least one of the plurality of on-chip modules.
8. The method of claim 7 , further comprising:
determining a difference between the first signal and the second signal.
9. The method of claim 8 , further comprising:
reporting the determined difference if the determined difference is non-zero.
10. The method according to claim 8 , further comprising:
reporting the second signal indicative of the power status of said at least one of the plurality of on-chip modules if the determined difference is non-zero.
11. The method of claim 1 , further comprising:
generating, based on the clock signal and the data signal, a list of the highest power consuming on-chip modules of the plurality of on-chip modules.
12. The method of claim 1 , wherein active bits in the data signal represent current power consumption within a specific on-chip module in the plurality of on-chip modules.
13. An apparatus for monitoring operating status of a plurality of modules within a chip, the apparatus comprising:
a power rail configured to supply power to the modules;
a plurality of resistors coupled to the power rail and the modules; and
a power analyzer module coupled to an output port, wherein the power analyzer module is configured to:
receive a first plurality of signals indicative of a power status of the modules, and
generate a clock signal and a data signal, wherein a predetermined number of clock cycles of the data signal represent a power status of a specific module in the plurality of modules.
14. The apparatus of claim 13 , wherein the power analyzer module is further configured to communicate the clock signal and the data signal via a serial bus.
15. The apparatus of claim 13 , wherein the power analyzer module is further configured to communicate the clock signal and the data signal via at least one of a plurality of pin connections on the chip.
16. The apparatus of claim 13 , wherein the data signal comprises sequential power status information for the plurality of modules.
17. The apparatus of claim 13 , wherein the power analyzer module is further configured to:
receive a second plurality of signals indicative of a second power status of the modules;
determine a difference between the first plurality of signals and the second plurality of signals; and
output the difference in response to determining that the difference is not zero.
18. The apparatus of claim 13 , wherein the first plurality of signals contain signals corresponding to voltage drops across the plurality of resistors.
19. The apparatus of claim 13 , further comprising a plurality of light emitting diodes (LEDs) coupled to the output port, wherein the LEDs are configured to display power consumption information regarding the modules.
20. The apparatus of claim 13 , wherein respective portions in a plurality of portions of the data signal contain power consumption information regarding respective modules in the plurality of modules.
21. A system on a chip for monitoring operating status of a plurality of powered on-chip modules, the system comprising:
a plurality of resistors coupled to the powered on-chip modules, wherein a first resistor in the plurality of resistors is coupled to a first on-chip module in the plurality of powered on-chip modules, and wherein a second resistor in the plurality of resistors is coupled to a second on-chip module in the plurality of powered on-chip modules; and
a power analyzer module, wherein the power analyzer module is configured to:
receive a first plurality of signals containing first power status information regarding the powered on-chip modules, and wherein the first plurality of signals includes a first signal indicating a voltage drop across the first resistor, and a second signal indicating a voltage drop across the second resistor, and
generate a clock signal and a data signal, wherein a predetermined number of clock cycles of the data signal represent a power status of a specific on-chip module in the plurality of powered on-chip modules;
an output port coupled to the power analyzer module, wherein the output port is configured to receive the output signal; and
a plurality of light emitting diodes (LEDs) coupled to the output port, wherein the LEDs are configured to display power consumption information based on the output signal.
22. The system of claim 21 , wherein the power analyzer module is further configured to:
receive a second plurality of signals containing second power status information regarding the powered on-chip modules;
determine a difference between the first plurality of signals and the second plurality of signals; and
output the difference in response to determining that the difference is not zero.
23. The system of claim 21 , further comprising:
a processor;
a memory;
a security module; and
a hardware accelerator.
24. The system of claim 21 , further comprising:
a voice input module;
a voice output module; and
a voice coder module.