IP Library Granted Patent US 7,605,009
Granted Patent B2
US 7,605,009 · App. 11/763,444 · Granted Oct 20, 2009

Method of fabrication MEMS integrated circuits

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Quick Facts
Patent No.
US 7,605,009
App. No.
11/763,444
Granted
Oct 20, 2009
Kind
B2
Abstract

A method of fabricating a plurality of MEMS integrated circuits from a wafer having a MEMS layer formed on a frontside thereof and a polymer coating over said MEMS layer, said polymer coating having a plurality of frontside dicing streets defined therethrough, said method comprising the steps of: (a) releasably attaching a first holding means to said polymer coating; and (b) performing at least one operation on a backside of the wafer, said at least one operation including etching a plurality of backside dicing streets through the wafer, each backside dicing street meeting with a respective frontside dicing street, thereby providing the plurality of MEMS integrated circuits releasably attached to said first holding means, wherein each MEMS integrated circuit comprises a respective polymer coating.

Claims (40)

1. A method of fabricating a plurality of MEMS integrated circuits from a wafer having a MEMS layer formed on a frontside thereof and a polymer coating over said MEMS layer, said polymer coating having a plurality of frontside dicing streets defined therethrough, said method comprising the steps of:

(a) releasably attaching a first holding means to said polymer coating; and

(b) performing at least one operation on a backside of the wafer, said at least one operation including etching a plurality of backside dicing streets through the wafer, each backside dicing street meeting with a respective frontside dicing street, thereby providing the plurality of MEMS integrated circuits releasably attached to said first holding means, wherein each MEMS integrated circuit comprises a respective polymer coating, said polymer coating being comprised of a polymerized siloxane.

2. The method of claim 1 , wherein said polymer coating is resistant to removal by an oxidative plasma.

3. The method of claim 1 , wherein said polymer coating is hydrophobic.

4. The method of claim 1 , wherein the polymer coating has a Young's modulus of less than 1000 MPa.

5. The method of claim 1 , wherein said polymer coating is photopatternable.

6. The method of claim 1 , wherein the polymer coating is comprised of polydimethylsiloxane (PDMS).

7. The method of claim 1 , wherein said MEMS layer comprises a plurality of inkjet nozzle assemblies, and said method provides a plurality of printhead integrated circuits.

8. The method of claim 1 , wherein said first holding means is releasably attached by means of an adhesive tape.

9. The method of claim 1 , wherein said first holding means is a handle wafer.

10. The method of claim 1 , further comprising the step of removing said integrated circuits from said first holding means.

11. The method of claim 1 , comprising the further steps of:

(c) releasably attaching a second holding means to said backside of the wafer; and

(d) removing the first holding means to provide the plurality of MEMS integrated circuits releasably attached to said second holding means.

12. The method of claim 1 , wherein said frontside is subjected to said oxidative plasma after step (d).

13. The method of claim 11 , wherein said second holding means is selected from the group comprising: a handle wafer and a wafer film frame.

14. The method of claim 2 , which includes the step of subjecting said wafer to an oxidative plasma for removing sacrificial material in the MEMS layer.

15. The method of claim 7 , wherein said polymer coating has a plurality of nozzle openings defined therethrough, each of said nozzle openings being aligned with a nozzle opening of a respective inkjet nozzle assembly.

16. The method of claim 7 , wherein step (b) comprises performing at least one operation selected from the group comprising:

backside wafer thinning;

backside etching of ink supply channels to provide a fluidic connection between said backside and said inkjet nozzle assemblies; and

subjecting said backside to an oxidative plasma.

17. The method of claim 8 , wherein said adhesive tape is a UV release tape or a thermal release tape.

18. The method of claim 16 , wherein said backside wafer thinning comprises one or more of:

wafer grinding; and

plasma etching.

19. A method of fabricating a plurality of MEMS integrated circuits from a wafer having a MEMS layer formed on a frontside thereof, said method comprising the steps of:

(a) applying a polymer coating over said MEMS layer;

(b) defining a plurality of frontside dicing streets through said polymer coating;

(c) releasably attaching a first holding means to said polymer coating; and

(d) performing at least one operation on a backside of the wafer, said at least one operation including etching a plurality of backside dicing streets through the wafer, each backside dicing street meeting with a respective frontside dicing street, thereby providing the plurality of MEMS integrated circuits releasably attached to said first holding means, wherein each MEMS integrated circuit comprises a protective polymer coating, said polymer coating being comprised of a polymerized siloxane.

20. A method of fabricating a plurality of MEMS integrated circuits from a wafer having a MEMS layer formed on a frontside thereof and a polymer coating over said MEMS layer, said polymer coating having a plurality of frontside dicing streets defined therethrough, said method comprising the steps of:

(a) releasably attaching a first holding means to said polymer coating; and

(b) performing at least one operation on a backside of the wafer, said at least one operation including etching a plurality of backside dicing streets through the wafer, each backside dicing street meeting with a respective frontside dicing street, thereby providing the plurality of MEMS integrated circuits releasably attached to said first holding means, wherein each MEMS integrated circuit comprises a respective polymer coating, said polymer coating being comprised of perfluorinated polyethylene (PFPE).

21. A method of fabricating a plurality of MEMS integrated circuits from a wafer having a MEMS layer formed on a frontside thereof, said method comprising the steps of:

(a) applying a polymer coating over said MEMS layer;

(b) defining a plurality of frontside dicing streets through said polymer coating;

(c) releasably attaching a first holding means to said polymer coating; and

(d) performing at least one operation on a backside of the wafer, said at least one operation including etching a plurality of backside dicing streets through the wafer, each backside dicing street meeting with a respective frontside dicing street, thereby providing the plurality of MEMS integrated circuits releasably attached to said first holding means, wherein each MEMS integrated circuit comprises a protective polymer coating, said polymer coating being comprised of perfluorinated polyethylene (PFPE).

Assignments (3)
CHANGE OF NAME Recorded Jun 25, 2014
From: ZAMTEC LIMITED
To: MEMJET TECHNOLOGY LIMITED
Reel/Frame 033244/0276 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2013
From: SILVERBROOK RESEARCH PTY. LIMITED
To: ZAMTEC LIMITED
Reel/Frame 031504/0149 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2007
From: MCAVOY, GREGORY JOHN; SILVERBROOK, KIA; KERR, EMMA ROSE; BAGNAT, MISTY; LAWLOR, VINCENT PATRICK
To: SILVERBROOK RESEARCH PTY LTD
Reel/Frame 019439/0871 →