Thin film transistor array panel and method of manufacture
View Patent ↗A thin film transistor array panel includes a gate line formed on a substrate, an interlayer insulating film formed on the gate line and having an opening, a gate insulator formed in the opening, a data line formed on the interlayer insulating film and including a first conductive layer made of a transparent conductive oxide and a second conductive layer made of a metal, a source electrode connected to the data line and made of a transparent conductive oxide, a drain electrode facing the source electrode and made of a transparent conductive oxide, a pixel electrode connected to the drain electrode, and an organic semiconductor contacting the source electrode and the drain electrode.
1. A thin film transistor array panel, comprising:
a gate line formed on a substrate;
an interlayer insulating film formed on the gate line and having an opening;
a gate insulator formed in the opening;
a data line formed on the interlayer insulating film and including a first conductive layer comprising a transparent conductive oxide and a second conductive layer comprising a metal;
a source electrode connected to the data line and comprising a transparent conductive oxide;
a drain electrode facing the source electrode and comprising a transparent conductive oxide;
a pixel electrode connected to the drain electrode; and
an organic semiconductor contacting the source electrode and the drain electrode.
2. The thin film transistor array panel of claim 1 , wherein the transparent conductive oxide is ITO or IZO.
3. The thin film transistor array panel of claim 2 , wherein the metal comprises at least one of molybdenum (Mo), a molybdenum alloy, chromium (Cr), a chromium alloy, aluminum (Al), an aluminum alloy, copper (Cu), a copper alloy, silver (Ag), and a silver alloy.
4. The thin film transistor array panel of claim 1 , wherein the opening comprises a first opening and a second opening that is larger than the first opening, and the first opening and the second opening may have the gate insulator and the organic semiconductor, respectively, formed therein.
5. The thin film transistor array panel of claim 1 , further comprising a protective member covering the organic semiconductor.
6. A thin film transistor array panel, comprising:
a gate line formed on a substrate and including a gate electrode;
a data line intersecting the gate line and including a first conductive layer and a second conductive layer;
a source electrode connected to the data line;
a pixel electrode including a drain electrode facing the source electrode; and
an organic semiconductor contacting the source electrode and the drain electrode, wherein the first conductive layer of the data line, the source electrode, and the pixel electrode comprise the same material.
7. The thin film transistor array panel of claim 6 , wherein the first conductive layer and the second conductive layer comprise materials with different etching selectivity ratios.
8. The thin film transistor array panel of claim 6 , wherein the first conductive layer of the data line, the source electrode, and the pixel electrode comprise a transparent conductive oxide, and the second conductive layer comprises a metal.
9. The thin film transistor array panel of claim 6 , further comprising an interlayer insulating film formed between the gate line and the data line, wherein the interlayer insulating film has a first opening and a second opening larger than the first opening.
10. The thin film transistor array panel of claim 9 , further comprising a gate insulator formed in the first opening and contacting the gate electrode, the source electrode, and the drain electrode.
11. The thin film transistor array panel of claim 6 , wherein the first conductive layer of the data line is disposed on the same layer with the source electrode and the pixel electrode.