Semiconductor memory device storing redundant replacement information with small occupation area
View Patent ↗Column redundancy data storage circuit blocks storing column redundancy data for repairing defective columns are arranged in correspondence to memory cell array blocks, respectively. The storage data of the column redundancy data storage circuits is transferred to redundancy data hold circuits arranged in spare column decoder bands adjacent to the data paths for transferring internal data, and are decoded for selection of a page in the spare decoder bands in column access. Therefore, it is possible to reduce the occupation area of a fuse program circuit which programs redundancy data for repairing a defective column.
1. A semiconductor memory device comprising:
a plurality of memory array blocks, each block having a plurality of memory cells arranged in rows and columns;
a plurality of redundancy data storage circuits, distributively arranged, corresponding to and along regions having corresponding memory array blocks placed thereon, each data storage circuit individually storing redundancy data for specifying a defective column of a corresponding memory array block, each of the redundancy data storage circuits including (i) a program circuit for programming and storing the redundancy data of the corresponding memory array block and (ii) a hold circuit receiving and holding storage data of the program circuit, the program circuit and the hold circuit being arranged oppositely with respect to the corresponding memory array block; and
a plurality of row decoder circuits arranged in correspondence with the memory array blocks and on an opposite side of the corresponding memory array blocks from the corresponding redundancy data storage circuits for the corresponding memory array blocks, each row decoder circuit decoding a received address signal to select an addressed row in the corresponding memory array block.
2. A semiconductor memory device comprising:
a plurality of memory array blocks, each block having a plurality of memory cells arranged in rows and columns;
a plurality of redundancy data storage circuits, distributively arranged corresponding to and along regions having corresponding memory array blocks placed thereon, each data storage circuit individually storing redundancy data for specifying a defective column of a corresponding memory array block, each of the redundancy data storage circuits including a program circuit, located outside the region of a corresponding memory block, for programming and storing the redundancy data for the defective column of the corresponding memory array block; and
a plurality of row decoder circuits arranged in correspondence with the memory array blocks and on an opposite side of the corresponding memory array blocks from the corresponding redundancy data storage circuits for the corresponding memory array blocks, each row decoder circuit decoding a received address signal to select an addressed row in the corresponding memory block.
3. The semiconductor memory device according to claim 2 , wherein each redundancy data storage circuit further comprises a hold circuit receiving and holding storage data of the program circuit.