Synchronous global controller for enhanced pipelining
View Patent ↗The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.
1. A memory device comprising:
at least one local memory block; and
a global controller coupled to at least said local memory block and adapted to manage timing of read and write operations; and
wherein each of the read and write operations are completed in a single cycle, wherein said single cycle is faster than an external clock cycle.
2. The memory device of claim 1 , wherein said global controller is synchronously controlled.
3. The memory device of claim 1 , wherein said global controller is further adapted to extend a portion of a clock pulse.
4. The memory device of claim 1 , wherein said local memory block comprises at least one memory cell.
5. The memory device of claim 1 , wherein said local memory block comprises at least one local decoder.
6. The memory device of claim 1 , wherein said local memory block comprises at least one local sense amp.
7. The memory device of claim 1 , wherein said local memory block comprises at least one local controller.
8. A method for processing read and write operations in a memory architecture having a synchronous global controller, the method comprising:
generating control signals; and
managing timing during the read and write operations;
wherein each of the read and write operations are completed in a single cycle, wherein said single cycle is faster than an external clock cycle.
9. The method of claim 8 , wherein managing said timing during the read and write operation includes skewing at least one clock pulse.
10. The method of claim 8 , wherein said global controller is synchronously controlled.
11. The method of claim 8 , wherein said global controller is further adapted to extend a portion of a clock pulse.
12. The method of claim 8 , wherein said local memory block comprises at least one memory cell.
13. The method of claim 8 , wherein said local memory block comprises at least one local decoder.
14. The method of claim 8 , wherein said local memory block comprises at least one local sense amp.
15. The method of claim 8 , wherein said local memory lock comprises at least one local controller.