Data decoding method and apparatus and receiver and communication system applying the same

1. A receiver applying High Speed Downlink Packet Access technology, the receiver comprising:

a memory for temporarily holding information bits, which are receive data strings, and first check bits and second check bits, which are reliability information of the information bits;

a first rate dematch apparatus for performing first rate dematch processing defined by the High-Speed Downlink Packet Access on the first check bits and the second check bits;

a memory group including memories each holding the information bits supplied through the first rate dematch apparatus and the first check bits and second check bits having undergone the first rate dematch processing and outputting the information bits, first check bits and second check bits at predetermined times;

a decoder for decoding and reconstructing receive data by using the information bits, first check bits and second check bits output from the memory group; and

a controller for, in synchronization with the output of the information bits from the memory group to the decoder, outputting the first check bits corresponding to the information bits from the memory group to the decoder, causing the first rate dematch apparatus to perform the first rate dematch processing on the second check bits, storing the first rate dematch processing result to the memory group, and, after the end of an output of the first check bits from the memory group and in synchronization with an output of the information bits from the memory group to the decoder, outputting the second check bits corresponding to the first check bits and the information bits from the memory group to the decoder.

2. A receiver according to claim 1 ,

wherein the memory group includes:

an information bit memory for holding the information bits;

a first check bit memory for holding the first check bits; and

a second check bit memory for holding the second check bits.

3. A receiver applying High Speed Downlink Packet Access technology, the receiver comprising:

a memory for temporarily holding information bits, which are receive data strings, and first check bits and second check bits, which are reliability information of the information bits;

a first rate dematch apparatus for performing first rate dematch processing defined by the High-Speed Downlink Packet Access on the first check bits and the second check bits;

a memory group including memories each holding the first check bits and second check bits having undergone the first rate dematch processing and outputting the first check bits and second check bits at predetermined times;

a decoder for decoding and reconstructing receive data by using the information bits, first check bits and second check bits;

a switch for supplying to the decoder the information bits output from the memory and supplying to the first rate dematch apparatus the first check bits and second check bits output from the memory; and

a controller for causing the first rate dematch apparatus to perform the first rate dematch processing on the first check bits and second check bits, storing the first rate dematch processing result to the memory group, and, in synchronization with an output of the information bits from the memory to the decoder, outputting the first check bits and second check bits corresponding to the information bits from the memory group to the decoder.

4. A receiver according to claim 3 ,

wherein the memory group includes:

a first check bit memory for holding the first check bits; and

a second check bit memory for holding the second check bits.

5. A receiver applying High Speed Downlink Packet Access technology, the receiver comprising:

a first memory group including multiple memories for holding information bits, which are receive data strings, in unit length of encoding processing and holding first check bits and second check bits, which are reliability information of the information bits;

a first rate dematch apparatus for performing first rate dematch processing defined by the High-Speed Downlink Packet Access on the first check bits and the second check bits;

a second memory group including memories each holding the first check bits and second check bits having undergone the first rate dematch processing and outputting the first check bits and second check bits at predetermined times;

a decoder group including multiple decoders corresponding to the unit of encoding processing and decoding and reconstructing receive data by using the information bits, first check bits and second check bits;

a switch group including multiple switches for supplying to the corresponding decoder the information bits output from the memory and supplying to the first rate dematch apparatus the first check bits and second check bits output from the memory; and

a controller for causing the first rate dematch apparatus to perform the first rate dematch processing on the first check bits and second check bits, storing the first rate dematch processing result to the second memory group, and, in synchronization with an output of the information bits from the memory to the decoder, outputting the first check bits and second check bits corresponding to the information bits from the second memory group to the decoder group.

6. A receiver according to claim 5 ,

wherein the second memory group includes:

multiple first check bit memories, corresponding to the decoders, for holding the first check bits; and

multiple second check bit memories, corresponding to the decoders, for holding the second check bits.

7. A communication system applying High-Speed Downlink Packet Access technology and comprising a receiver according to claim 1 .

8. A communication system applying High-Speed Downlink Packet Access technology and comprising a receiver according to claim 3 .

9. A communication system applying High-Speed Downlink Packet Access technology and comprising a receiver according to claim 5 .