Reset-tolerant authentication device

1. An authentication device comprising:

a processor having a reset input;

a trigger source coupled to the reset input; and

interface circuitry for outputting codes generated by the processor;

wherein the processor is configured to analyze a given reset applied to the reset input to determine if the reset is an inadvertent reset or a reset generated by the trigger source, and to generate a code responsive to the reset if the reset is determined to be a reset generated by the trigger source; and

wherein the processor analyzes the given reset by examining information stored in a register file of the processor to identify a particular one of a number of different possible causes for the given reset.

2. The device of claim 1 wherein the trigger source comprises a trigger button having an associated switch that when actuated supplies a reset to the reset input.

3. The device of claim 1 wherein the processor is operative in at least two different modes including a low-power sleep mode and a normal operation mode.

4. The device of claim 3 wherein the processor is maintained in the low-power sleep mode if the given reset is received while the processor is in that mode and the given reset is determined to be an inadvertent reset.

5. The device of claim 3 wherein the processor transitions from the low-power sleep mode to the normal operation mode if the given reset is received while the processor is in the low-power sleep mode and the given reset is determined to be a reset generated by the trigger source.

6. The device of claim 1 wherein the trigger source comprises an additional processor.

7. The device of claim 1 further comprising power-up circuitry coupled to the trigger source.

8. The device of claim 7 wherein the power-up circuitry comprises a resistor-capacitor circuit.

9. The device of claim 8 wherein the power-up circuitry comprises a resistor coupled between a supply voltage and the reset input, and a capacitor coupled between the reset input and a ground potential.

10. The device of claim 9 wherein the power-up circuitry comprises a diode connected in parallel with the resistor to provide voltage level tracking for the supply voltage.

11. The device of claim 7 wherein a first terminal of the trigger source is coupled to the reset input and wherein the power-up circuitry comprises a current limiter resistor coupled between a second terminal of the trigger source and one of a supply voltage and a ground potential.

12. The device of claim 1 wherein the different possible causes for the given reset identified by the information stored in the register file of the processor comprise one or more of an initial application of power to the device, expiration of an internal timer, and a sensor reaching a predetermined limit.

13. The device of claim 1 wherein actuation of the trigger source coupled to the reset input causes the processor to generate the code.

14. An authentication device comprising:

a processor having a reset input;

a trigger source coupled to the reset input; and

interface circuitry for outputting codes generated by the processor;

wherein the processor is configured to analyze a given reset applied to the reset input to determine if the reset is an inadvertent reset or a reset generated by the trigger source, and to generate a code responsive to the reset if the reset is determined to be a reset generated by the trigger source; and

wherein the processor comprises an internal random access memory and the processor is configured such that a given reset applied to the reset input does not affect contents of the internal random access memory.

15. An authentication device comprising:

a processor having a reset input;

a trigger source coupled to the reset input; and

interface circuitry for outputting codes generated by the processor;

wherein the processor is configured to analyze a given reset applied to the reset input to determine if the reset is an inadvertent reset or a reset generated by the trigger source, and to generate a code responsive to the reset if the reset is determined to be a reset generated by the trigger source;

the device further comprising power-up circuitry coupled to the trigger source;

wherein the power-up circuitry comprises a first resistor coupled between the reset input and a supply voltage and a second resistor coupled between the reset input and a ground potential.

16. A method for use in an authentication device comprising a processor and a trigger source coupled to a reset input of the processor, the method comprising the steps of:

analyzing a given reset applied to the reset input to determine if the reset is an inadvertent reset or a reset generated by the trigger source; and

outputting a code responsive to the reset if the reset is determined to be a reset generated by the trigger source;

wherein the analyzing step utilizes information stored in a register file of the processor to identify a particular one of a number of different possible causes for the given reset.

17. The method of claim 16 wherein the processor is operative in at least two different modes including a normal operation mode and a low-power sleep mode.

18. The method of claim 17 further comprising the step of maintaining the processor in the low-power sleep mode if the given reset is received while the processor is in that mode and the given reset is determined to be an inadvertent reset.

19. The method of claim 17 further comprising the step of transitioning the processor from the low-power sleep mode to the normal operation mode if the given reset is received while the processor is in the low-power sleep mode and the given reset is determined to be a reset generated by the trigger source.

20. A processor-readable storage medium storing one or more software programs, wherein the one or more software programs when executed by the processor of the authentication device implement the steps of the method of claim 16 .

21. An authentication system comprising:

a plurality of authentication devices;

at least one host device configured for communication with one or more of the authentication devices; and

an authentication server configured for communication with the host device;

wherein at least one of the authentication devices comprises a processor and a trigger source coupled to a reset input of the processor, said authentication device being configured to analyze a given reset to determine if the reset is an inadvertent reset or a reset generated by the trigger source, and to output a code responsive to the reset if the reset is determined to be a reset generated by the trigger source;

wherein the code is provided to the host device and communicated by the host device to the authentication server for authentication; and

wherein the processor analyzes the given reset by examining information stored in a register file of the processor to identify a particular one of a number of different possible causes for the given reset.

22. The system of claim 21 wherein the analysis of the given reset further includes determining if there is a legitimate cause of the given reset by examining sets of one or more bits of state information stored in one or more registers of the register file of the processor, and wherein each of the sets of one or more bits of state information being in a particular configuration is representative of a different possible legitimate cause for the given reset.

23. The system of claim 21 wherein the different possible causes for the given reset identified by the information stored in the register file of the processor comprise one or more of an initial application of power to the device, expiration of an internal timer, and a sensor reaching a predetermined limit.

24. An authentication device comprising:

a processor having a reset input;

a trigger source coupled to the reset input; and

interface circuitry for outputting codes generated by the processor;

wherein the processor is configured to analyze a given reset applied to the reset input to determine if the reset is an inadvertent reset or a reset generated by the trigger source, and to generate a code responsive to the reset if the reset is determined to be a reset generated by the trigger source; and

wherein the analysis of the given reset further includes determining if there is a legitimate cause of the given reset by examining sets of one or more bits of state information stored in one or more registers of a register file of the processor, and wherein each of the sets of one or more bits of state information being in a particular configuration is representative of a different possible legitimate cause for the given reset.

25. The device of claim 24 wherein the analysis of the given reset further comprises identifying the given reset as an inadvertent reset if the given reset does not produce one or more bits of state information in one of the particular configurations representative of the different possible legitimate causes for the given reset.

26. An authentication device comprising:

a processor having a reset input;

a trigger source coupled to the reset input; and

interface circuitry for outputting codes generated by the processor;

wherein the processor is configured to analyze a given reset applied to the reset input to determine if the reset is an inadvertent reset or a reset generated by the trigger source, and to generate a code responsive to the reset if the reset is determined to be a reset generated by the trigger source; and

wherein the analysis of the given reset further comprises reading at least one of a signature and a checksum from a random access memory and comparing said at least one of a signature and a checksum to at least one of a corresponding respective hardcoded signature and a computed checksum.

27. The device of claim 26 wherein the processor is initialized prior to determining if the given reset is an inadvertent reset or a reset generated by the trigger source if said at least one of a signature and a checksum read from the random access memory does not match said at least one of the corresponding respective hardcoded signature and computed checksum.