Granted Patent B1

US 7,389,577 · App. 11/768,883 · Granted Jun 24, 2008

Abstract

Claims (25)

1. A method to fabricate a tunneling magnetoresistive (TMR) read transducer, comprising the acts of:

depositing an insulative layer on a wafer substrate;

depositing a bottom lead over the insulative layer;

depositing a laminated TMR layer over the bottom lead, the laminated TMR layer comprising a plurality of laminates;

defining a TMR sensor having a stripe height in the TMR layer;

defining a parallel resistor in the TMR layer;

defining first and second shunt resistors in the TMR layer;

depositing a top lead over the TMR sensor;

electrically connecting the parallel resistor to the bottom lead and to the top lead;

electrically connecting the first shunt resistor to the bottom lead and the wafer substrate;

electrically connecting the second shunt resistor to the top lead and the wafer substrate.

2. The method of claim 1 wherein the acts of defining the sensor stripe height, defining the parallel resistor, and defining the first and second shunt resistors each include etching the TMR layer.

3. The method of claim 2 wherein the act of defining the sensor stripe height is accomplished using a vacuum manufacturing apparatus and by an etching technique, and wherein the acts of defining the parallel resistor and defining the first and second shunt resistors are accomplished using the same vacuum manufacturing apparatus and by the same etching technique.

4. The method of claim 2 wherein the steps of defining the sensor stripe height, defining the parallel resistor, and defining the first and second shunt resistors are performed simultaneously in a single process step.

5. The method of claim 1 wherein a resistance of the first shunt resistor is within ±10% of a resistance of the second shunt resistor.

6. The method of claim 1 wherein each of the first and second shunt resistors is defined to have a shunt resistor path width and a shunt resistor path length, and wherein the shunt resistor path width and the shunt resistor path length are chosen so that each of the first and second shunt resistors has a resistance greater than 1 kΩ.

7. The method of claim 6 wherein the each of first and second shunt resistors is defined to have a serpentine shape.

8. The method of claim 6 wherein the shunt resistor path width is chosen to be in the range 0.2 to 5 microns.

9. The method of claim 6 wherein the shunt resistor path length is chosen to be in the range 50 microns to 50 mm.

10. The method of claim 1 wherein the parallel resistor is defined to have a parallel resistor path width and a parallel resistor path length, and wherein the parallel resistor path width and the parallel resistor path length are chosen so that the parallel resistor has a resistance in the range 0.1 to 5 kΩ.

11. The method of claim 10 wherein the parallel resistor path width is chosen to be in the range 0.2 to 5 microns.

12. The method of claim 10 wherein the parallel resistor path length is chosen to be in the range 5 to 1250 microns.

13. The method of claim 1 wherein the plurality of laminates includes a barrier laminate that comprises an oxide of aluminum, titanium, or magnesium, the oxide being electrically insulative in bulk.

14. The method of claim 1 wherein the plurality of laminates includes a barrier laminate that comprises a nitride of aluminum, silicon, or niobium, the nitride being electrically insulative in bulk.

15. The method of claim 1 wherein the laminated TMR layer has a resistance area product no greater than 10 Ω* 0 μm 2 .

Assignments (8)