IP Library Granted Patent US 7,388,400
Granted Patent B2
US 7,388,400 · App. 11/768,981 · Granted Jun 17, 2008

Semiconductor integrated circuits with power reduction mechanism

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Quick Facts
Patent No.
US 7,388,400
App. No.
11/768,981
Granted
Jun 17, 2008
Kind
B2
Abstract

A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power lines and a first switching element for each circuit block. Each circuit block includes a first MOS transistor in which a leakage current flows even under a condition that a gate voltage is equal to a source voltage. Each of the first switching elements controls the leakage current flowing through a corresponding first MOS transistor of each circuit block. Also, while one of the first switching elements is controlled to reduce the leakage current flowing through the circuit block relating to one of the first switching elements, another one of the first switching elements is controlled to allow current to flow through the circuit block relating to another one of the first switching elements. In addition, current which is allowed to flow by the another one of the first switching elements is sufficient to permit the circuit block relating to another one of the first switching elements to logically operate.

Claims (28)

1. A semiconductor integrated circuit operating at an operating voltage of which the absolute value is about 2.5 V or below, comprising:

a plurality of circuit blocks to which operation voltage is supplied by a first power line and a second power line; and

a first switching element for each said circuit block;

wherein each circuit block includes a first MOS transistor in which a leakage current flows between a drain and a source of said first MOS transistor, including under a condition that a gate voltage is equal to a source voltage in said first MOS transistor,

wherein each of said first switching elements is adapted to control the leakage current flowing through a corresponding one of said first MOS transistors of said each circuit block,

wherein, while one of said first switching elements is controlled to reduce said leakage current flowing through the circuit block relating to one of said first switching elements, another one of said first switching elements is controlled to allow current to flow thorough the circuit block relating to another one of said first switching elements, and

wherein said current which is allowed to flow by said another one of said first switching elements is sufficient to permit said circuit block relating to another one of said first switching elements to logically operate.

2. A semiconductor integrated circuit operating at an operating voltage of which the absolute value is about 2.5 V or below, comprising:

a plurality of circuit blocks to which operation voltage is supplied by a first power line and a second power line; and

a first switching element for each said circuit block;

wherein each circuit block includes a first MOS transistor in which a leakage current flows between a drain and a source of said first MOS transistor, including under a condition that a gate voltage is equal to a source voltage in said first MOS transistor,

wherein each of said first switching elements is adapted to control the leakage current flowing through a corresponding one of said first MOS transistors of said each circuit block,

wherein said each first switching element is a second MOS transistor of which the source/drain path is connected between said first power line and said circuit block relating to said each first switching element; and

wherein, while at least one of the circuit blocks is selected, said first switching element controlling said at least one of the circuit blocks is adapted to allow the voltage of said first power line to be applied to said circuit block through said first switching element, while the second MOS transistors of the first switching element controlling the circuit blocks not selected are turned off.

3. A semiconductor integrated circuit operating at an operating voltage of which the absolute value is about 2.5 V or below, comprising:

a plurality of circuit blocks to which operation voltage is supplied by a first power line and a second power line;

wherein each circuit block includes a first MOS transistor in which a leakage current flows between the drain and the source of said first MOS transistor, including under a condition that a gate voltage is equal to a source voltage in said first MOS transistor; and

a plurality of first switching elements,

wherein each first switching element corresponding to each circuit block is adapted to control the leakage current flowing through a corresponding one of said first MOS transistors of said each circuit block,

wherein, while one of said first switching elements is controlled to reduce said leakage current flowing through the circuit block corresponding to one of said first switching elements, another one of said first switching elements is controlled to allow current to flow through the circuit block corresponding to another one of said first switching elements, and

where said current which is allowed to flow by said another one of said first switching elements is sufficient to permit said circuit block corresponding to another one said first switching elements to logically operate.

4. A semiconductor integrated circuit operating at an operating voltage of which the absolute value is about 2.5 V or below, comprising:

a plurality of circuit blocks to which operation voltage is supplied by a first power line and a second power line,

wherein each circuit block includes a first MOS transistor in which a leakage current flows between a drain and a source of said first MOS transistor, including under a condition that a gate voltage is equal to a source voltage in said first MOS transistor; and

a plurality of first switching elements;

wherein each first switching element corresponding to said each circuit block is adapted to control the leakage current flowing through a corresponding one of said first MOS transistors of said each circuit block,

wherein said each first switching element is a second MOS transistor of which the source/drain path is connected between said first power line and said circuit block corresponding to said each first switching element; and

wherein, while at least one of the circuit blocks is selected, said first switching element controlling said at least one of the circuit blocks is adapted to allow the voltage of said first power line to be applied to said circuit block through said first switching element, while the second MOS transistors of the first switching element controlling the circuit blocks not selected are turned off.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: ELPIDA MEMORY, INC.
To: PS4 LUXCO S.A.R.L.
Reel/Frame 032899/0588 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2013
From: SAKATA, TAKESHI; ITOH, KIYOO; HORIGUCHI, MASASHI
To: HITACHI, LTD.
Reel/Frame 031543/0254 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2013
From: HITACHI, LTD.
To: ELPIDA MEMORY, INC.
Reel/Frame 031580/0157 →
SECURITY AGREEMENT Recorded Jul 29, 2013
From: PS4 LUXCO S.A.R.L.
To: ELPIDA MEMORY INC.
Reel/Frame 032414/0261 →