Thin film transistor substrate having electrode layers that are formed on insulating layer to cover common voltage line and grounding line

1. A thin film transistor substrate divided into a display area to display the image and a non-display beside the display area, the thin film transistor substrate comprising:

first and second gate driving chips and a data driving chip on the non-display area;

a common voltage line for an MPS (mass production system) test and a grounding line for the MPS (mass production system) test formed on the non-display area in parallel;

an insulating layer to cover the common voltage line for the MPS test and the grounding line for the MPS test; and

an electrode layer formed on the insulating layer corresponded to the common voltage line for the MPS test and the grounding line for the MPS test,

wherein the common voltage line for the MPS test, the insulating layer and the electrode layer forms a first capacitor, and the grounding line for the MPS test, the insulating layer and the electrode layer forms a second capacitor.

2. The thin film transistor substrate according to claim 1 , wherein the electrode layer comprises ITO (indium tin oxide) or IZO (indium zinc oxide).

3. The thin film transistor substrate according to claim 1 , wherein the insulating layer comprises a first insulating layer and a second insulating layer formed on the first insulating layer, and the first insulating layer comprises inorganic materials and the second insulating layer comprises organic materials.

4. The thin film transistor substrate according to claim 3 , further comprising a gate wire and a data wire crossed to each other and defining a pixel area, and being formed at the display area,

wherein the common voltage line for the MPS test and the grounding line for the MPS test are formed in a same material with the gate wire at the same time.

5. The thin film transistor substrate according to claim 4 , further comprising a gate insulating layer to cover the gate wire and a passivation layer to cover the data wire,

wherein the first insulating layer is formed in the same material with the gate insulating layer at the same time and the second insulating layer is formed in the same material with the passivation layer at the same time.

6. The thin film transistor substrate according to claim 5 , further comprising a pixel electrode covering the passivation layer at the pixel area,

wherein the electrode layer is formed in a same material with the pixel electrode at the same time.

7. The thin film transistor substrate according to claim 1 , wherein the common voltage line for the MP S test is a wire for testing whether a common voltage is applied to a common line.

8. The thin film transistor substrate according to claim 7 , wherein the common line in the display area is connected to the common voltage line for the MPS test through a LOG (line on glass) line.

9. The thin film transistor substrate according to claim 7 , wherein the common voltage line for the MPS test is used as a testing wire during an MPS test process and the common voltage line for the MPS test is used as a wire to distribute the common voltage to the common voltage line after cutting a mother substrate into each thin film transistor substrate.

10. The thin film transistor substrate according to claim 1 , wherein the grounding line for the MPS test is a wire to test whether substrate areas of the mother substrate are connected each other electrically.

11. The thin film transistor substrate according to claim 1 , wherein the grounding line for the MPS test is employed for grounding a static electricity preventing circuit after cutting a mother substrate into each thin film transistor substrate.