Serial communication input output interface engine

1. An apparatus comprising:

a processor;

a communication subsystem comprising an advance register;

a first buffer memory;

a second buffer memory; and

a serial controller operable to alternately swap access to the first buffer memory and the second buffer memory between the processor and the communication subsystem;

where wherein the advance register is operable to duplicate data written to a predetermined location of the first buffer memory when the first buffer memory is accessible to the processor, and

wherein the serial controller is further operable to:

receive a first clock signal indicative of a first operating frequency for the processor;

receive a second clock signal indicative of a second operating frequency for a serial device, the first operating frequency being different than the second operating frequency;

receive a synchronization signal having a frequency, the synchronization signal to account for the first operating frequency and the second operating frequency, the synchronization signal to synchronize operation of a serial communication interface engine between the processor and the serial device and the synchronization signal being indicative of a new processing period;

verify that no accesses to the first memory buffer and the second memory buffer are pending in response to the synchronization signal; and

swap access to the first buffer memory and the second buffer memory between the processor and the communication subsystem in response to verifying that no accesses to the first memory buffer and the second memory buffer are pending.

2. The apparatus of claim 1 , where the communication subsystem further comprises advance logic to monitor data written to the predetermined location of the first buffer memory.

3. The apparatus of claim 1 , where the communication subsystem further comprises a shift register section that is selectively configurable between data transmission and data reception.

4. The apparatus of claim 3 , where the shift register section further comprises an input register selectively coupled to the first buffer memory and the second buffer memory, the input register configured to receive data to be transmitted to the serial device.

5. The apparatus of claim 3 , where the shift register section further comprises a shift register coupled to the serial device, the shift register configured to receive data from the serial device.

6. The apparatus of claim 3 , where the shift register section further comprises an output register coupled to the shift register and to the controller, the output register configured to receive shift register data and to provide the shift register data to the controller.

7. A communication system comprising:

a processor;

a first buffer memory selectively coupled with the processor;

a second buffer memory selectively coupled with the processor;

serial controller coupled to a shift register section, the serial controller configured to perform an access swap of the first buffer memory and the second buffer memory between the processor and the serial controller;

an advance register coupled to the shift register section; and

address comparison logic operable to monitor when a data value is written into a predetermined location in the first buffer memory during a processing period and forward the data value to the advance register during the processing period that the data value is written into the predetermined location in the first buffer memory;

where wherein the shift register section is operable to obtain the data value from the advance register instead of from the first buffer memory, and transmit the data value, and

wherein the serial controller is further configured to:

receive a first clock signal indicative of a first operating frequency for the processor;

receive a second clock signal indicative of a second operating frequency for a serial device, the first operating frequency being different than the second operating frequency;

receive a synchronization signal having a frequency, the synchronization signal to account for the first operating frequency and the second operating frequency, the synchronization signal to synchronize operation of a serial communication interface engine between the processor and the serial device and the synchronization signal being indicative of a new processing period;

verify that no accesses to the first memory buffer and the second memory buffer are pending in response to the synchronization signal; and

swap access of the first buffer memory and the second buffer memory between the processor and the serial controller in response to verifying that no accesses to the first memory buffer and the second memory buffer are pending.

8. The communication system of claim 7 , where the advance register is one of multiple advance registers and the shift register section is one of multiple shift register sections.

9. The communication system of claim 7 where the shift register section comprises a multiplexer including a first input coupled to an input register and a second input coupled to the advance register.

10. The communication system of claim 9 where the multiplexer comprises an output coupled to a staging register, and where the shift register section is operable to transmit the data value from the staging register.

11. The communication system of claim 10 where the staging register comprises a shift register.

12. An apparatus comprising:

a data processor for providing data;

a serial subsystem including a serial controller that is configured to:

receive a first clock signal indicative of a first operating frequency for the data processor;

receive a second clock signal indicative of a second operating frequency for a serial device, the first operating frequency being different than the second operating frequency;

receive a synchronization signal having a frequency, the synchronization signal to account for the first operating frequency and the second operating frequency, the synchronization signal to synchronize operation of a serial communication interface engine between the processor and the serial device and the synchronization signal being indicative of a new processing period;

verify that no accesses to a first memory buffer and to a second memory buffer are pending; and

swap access to a first buffer memory and a second buffer memory between the data processor and the serial subsystem in response to verifying that no accesses to the first memory buffer and the second memory buffer are pending.

13. The apparatus of claim 12 , wherein the serial subsystem further comprises advance logic to monitor data written to a predetermined location of the first buffer memory.

14. The apparatus of claim 13 , wherein the serial subsystem further comprises a shift register section that is selectively configurable between data transmission and data reception.

15. The apparatus of claim 14 , wherein the shift register section further comprises an input register selectively coupled to the first buffer memory and the second buffer memory, the input register configured to receive data to be transmitted to the serial device.

16. The apparatus of claim 14 , where the shift register section further comprises a shift register coupled to the serial device, the shift register configured to receive data from the serial device.

17. The apparatus of claim 14 , wherein the shift register section further comprises an output register coupled to the shift register and to the controller, the output register configured to receive shift register data and to provide the shift register data to the controller.

18. The apparatus of claim 12 wherein the first buffer memory and the second buffer memory are each arranged to store digital samples of an audio signal.

19. The apparatus of claim 1 wherein the first buffer memory and the second buffer memory are each arranged to store digital samples of an audio signal.

20. The communication system of claim 7 wherein the first buffer memory and the second buffer memory are each arranged to store digital samples of an audio signal.